Equivalence Hooks: Debug Playbook

Debug playbook

Debug Playbook for Equivalence Hooks focuses on LEC pass rate, unresolved points, debug turnaround. The goal is to connect observed QoR movement to mechanism, ownership, and regression risk.

Synthesis debug finds the first causal drift, not the loudest downstream symptom.

Root-cause tree

ROOT-CAUSE TREE — Equivalence Hooks

LEC pass rate, unresolved points, debug turnaround regressed
        |
   same RTL/constraints tag?
     /              \
   no                yes
   |                  |
input drift      transform side-effect
 /    \             /         \
SDC    libs      mapping      physical estimate
diff   diff      choice       mismatch

1. Freeze baseline and regressed run manifests.

2. Verify RTL/SDC/library deltas before transform tuning.

3. Classify issue: constraints, mapping choice, physical estimate, or ECO side effect.

4. Pick one minimal reversible change.

5. Re-run full timing/area/power checks with ownership signoff.

Review memo template

STAFF SYNTHESIS REVIEW MEMO — Incremental & ECO Synthesis / Equivalence Hooks

1. Symptom
   - Watched metric: LEC pass rate, unresolved points, debug turnaround
   - Affected compile run: <tag/build ID>
   - Impacted path/class: <critical group / power lane / area lane>
   - Database tags: <RTL, SDC, libs, switches>

2. Mechanism hypothesis
   - Primary mechanism: Equivalence hooks align synthesis and ECO transformations with formal checking so aggressive optimization remains provably correct.
   - Competing hypothesis: <constraint drift, mapping choice, physical estimate mismatch>
   - Missing evidence: <report diff, dashboard trend, ownership board>

3. Proposed action
   - Minimal reversible change: <constraint patch, compile knob, ECO cell move>
   - Expected movement: <timing / area / power delta>
   - Regression risk: hold, power spike, leakage drift, formal mismatch

4. Signoff
   - Re-run artifact: LEC script, mismatch report, waivers log
   - Required owners: formal owner, synthesis owner, CAD owner
   - Final decision: merge, rollback, or escalate

Synthesis deep dive

Incremental and ECO synthesis protect schedule only with strict regression discipline.

Concept diagram

INCREMENTAL ECO LOOP

identify delta -> localized compile -> patch -> regression -> release

Metric graph

ECO CYCLE TIME

full compile      ███████████
incremental       █████

Reports and artifacts

• incremental reuse

• ECO patch list

• LEC status

• regression matrix

Mini case study

Localized compile cut turnaround 40%, but skipped LEC caused rollback.

Debug branches

• Reuse ratio is not enough

• Patch locality check

• Always include equivalence hooks

Senior review question

Ask: what evidence proves this QoR move is real and stable?

Key takeaways

• State exact run context (RTL, SDC, libs, switches) with every QoR claim.

• Re-run timing, area, and power regressions after each synthesis ECO.

Common pitfalls

• Comparing runs with mismatched constraints or library views.

• Timing-only fixes that violate power or area budgets.

• Skipping equivalence checks after structural changes.

Principal synthesis review addendum

Equivalence hooks align synthesis and ECO transformations with formal checking so aggressive optimization remains provably correct.

Metric: LEC pass rate, unresolved points, debug turnaround