Equivalence Hooks: Worked Example

Worked example

Worked Example for Equivalence Hooks focuses on LEC pass rate, unresolved points, debug turnaround. The goal is to connect observed QoR movement to mechanism, ownership, and regression risk.

A weekly compile reports LEC pass rate, unresolved points, debug turnaround regression. Instead of random knob tuning, start by proving whether input context changed and which mechanism dominates.

Sequence under inspection

SYNTHESIS FLOW — Equivalence Hooks

RTL + constraints
      |
      v
elaboration + checks
      |
      v
mapping + optimization
      |
      v
QoR reports (timing/area/power)
      |
      v
incremental ECO + regression

Primary metric: LEC pass rate, unresolved points, debug turnaround

Equivalence hook chain

synthesis/eco transform
      |
      v
mapping points + constraints
      |
      v
LEC proof / mismatch triage

1. Capture baseline and regressed artifact pair.

2. Confirm manifest parity (RTL, SDC, libs, switches).

3. Pin first metric drift and mechanism hypothesis.

4. Reproduce with LEC script, mismatch report, waivers log.

5. Apply one reversible fix and run matrix regression.

Did the fix hold?

BEFORE / AFTER QOR — Equivalence Hooks

QoR score
  0 |                     --- target zone
 -1 |        ● regression
 -2 |             ● baseline
 -0.5|                  ● after fix
    +----------------------------------> iteration

Validate timing + area + power, not one number.

Synthesis deep dive

Incremental and ECO synthesis protect schedule only with strict regression discipline.

Concept diagram

INCREMENTAL ECO LOOP

identify delta -> localized compile -> patch -> regression -> release

Metric graph

ECO CYCLE TIME

full compile      ███████████
incremental       █████

Reports and artifacts

• incremental reuse

• ECO patch list

• LEC status

• regression matrix

Mini case study

Localized compile cut turnaround 40%, but skipped LEC caused rollback.

Debug branches

• Reuse ratio is not enough

• Patch locality check

• Always include equivalence hooks

Senior review question

Ask: what evidence proves this QoR move is real and stable?

Key takeaways

• State exact run context (RTL, SDC, libs, switches) with every QoR claim.

• Re-run timing, area, and power regressions after each synthesis ECO.

Common pitfalls

• Comparing runs with mismatched constraints or library views.

• Timing-only fixes that violate power or area budgets.

• Skipping equivalence checks after structural changes.

Principal synthesis review addendum

Equivalence hooks align synthesis and ECO transformations with formal checking so aggressive optimization remains provably correct.

Metric: LEC pass rate, unresolved points, debug turnaround