Scenario: Retiming Debate: Debug Playbook

Debug playbook

Debug Playbook for Scenario: Retiming Debate focuses on frequency target miss versus latency and verification budget. The goal is to connect observed QoR movement to mechanism, ownership, and regression risk.

Synthesis debug finds the first causal drift, not the loudest downstream symptom.

Root-cause tree

ROOT-CAUSE TREE — Scenario: Retiming Debate

frequency target miss versus latency and verification budget regressed
        |
   same RTL/constraints tag?
     /              \
   no                yes
   |                  |
input drift      transform side-effect
 /    \             /         \
SDC    libs      mapping      physical estimate
diff   diff      choice       mismatch

1. Freeze baseline and regressed run manifests.

2. Verify RTL/SDC/library deltas before transform tuning.

3. Classify issue: constraints, mapping choice, physical estimate, or ECO side effect.

4. Pick one minimal reversible change.

5. Re-run full timing/area/power checks with ownership signoff.

Review memo template

STAFF SYNTHESIS REVIEW MEMO — Synthesis Interview Prep / Scenario: Retiming Debate

1. Symptom
   - Watched metric: frequency target miss versus latency and verification budget
   - Affected compile run: <tag/build ID>
   - Impacted path/class: <critical group / power lane / area lane>
   - Database tags: <RTL, SDC, libs, switches>

2. Mechanism hypothesis
   - Primary mechanism: Retiming debate evaluates whether register movement is safer than RTL pipeline edits under schedule and formal constraints.
   - Competing hypothesis: <constraint drift, mapping choice, physical estimate mismatch>
   - Missing evidence: <report diff, dashboard trend, ownership board>

3. Proposed action
   - Minimal reversible change: <constraint patch, compile knob, ECO cell move>
   - Expected movement: <timing / area / power delta>
   - Regression risk: hold, power spike, leakage drift, formal mismatch

4. Signoff
   - Re-run artifact: retiming option sheet, equivalence plan, risk matrix
   - Required owners: microarchitecture owner, synthesis owner, formal owner
   - Final decision: merge, rollback, or escalate

Synthesis deep dive

Interview readiness comes from repeatable QoR reasoning under pressure.

Concept diagram

INTERVIEW ANSWER SHAPE

context -> metric -> mechanism -> fix -> regression -> ownership

Metric graph

PANEL SCORING

clarity      ███████
mechanism    ██████
regression   █████

Reports and artifacts

• mock scorecard

• scenario debrief

• Q&A coverage

• framework adherence

Mini case study

Candidate improved by replacing tool-command answers with evidence-driven closure narratives.

Debug branches

• State assumptions first

• Defend option tradeoffs

• Close with rollback/regression

Senior review question

Ask: what evidence proves this QoR move is real and stable?

Key takeaways

• State exact run context (RTL, SDC, libs, switches) with every QoR claim.

• Re-run timing, area, and power regressions after each synthesis ECO.

Common pitfalls

• Comparing runs with mismatched constraints or library views.

• Timing-only fixes that violate power or area budgets.

• Skipping equivalence checks after structural changes.

Principal synthesis review addendum

Retiming debate evaluates whether register movement is safer than RTL pipeline edits under schedule and formal constraints.

Metric: frequency target miss versus latency and verification budget