Scenario: Retiming Debate: Design Space

Design space exploration

For Scenario: Retiming Debate, options trade QoR gain, risk, and schedule.

Option A — conservative

• Conservative constraints: helps predictability

• Risk: slower PPA gains

• Validate with: first-silicon safety

Option B — balanced

• Balanced QoR tuning: helps stable closure

• Risk: requires discipline

• Validate with: typical product mode

Option C — aggressive compile

• Aggressive compile push: helps fast timing recovery

• Risk: power/hold regressions

• Validate with: late schedule

Option D — structural change

• Structural RTL change: helps long-term fix

• Risk: schedule impact

• Validate with: recurring bottleneck

DESIGN SPACE — Scenario: Retiming Debate
QoR gain <-> regression risk <-> schedule pressure

Design pitfalls

• Single-metric optimization

• No rollback path

• Weak run comparability

Tradeoff curve

BEFORE / AFTER QOR — Scenario: Retiming Debate

QoR score
  0 |                     --- target zone
 -1 |        ● regression
 -2 |             ● baseline
 -0.5|                  ● after fix
    +----------------------------------> iteration

Validate timing + area + power, not one number.

Synthesis deep dive

Interview readiness comes from repeatable QoR reasoning under pressure.

Concept diagram

INTERVIEW ANSWER SHAPE

context -> metric -> mechanism -> fix -> regression -> ownership

Metric graph

PANEL SCORING

clarity      ███████
mechanism    ██████
regression   █████

Reports and artifacts

• mock scorecard

• scenario debrief

• Q&A coverage

• framework adherence

Mini case study

Candidate improved by replacing tool-command answers with evidence-driven closure narratives.

Debug branches

• State assumptions first

• Defend option tradeoffs

• Close with rollback/regression

Senior review question

Ask: what evidence proves this QoR move is real and stable?

Key takeaways

• State exact run context (RTL, SDC, libs, switches) with every QoR claim.

• Re-run timing, area, and power regressions after each synthesis ECO.

Common pitfalls

• Comparing runs with mismatched constraints or library views.

• Timing-only fixes that violate power or area budgets.

• Skipping equivalence checks after structural changes.

Principal synthesis review addendum

Retiming debate evaluates whether register movement is safer than RTL pipeline edits under schedule and formal constraints.

Metric: frequency target miss versus latency and verification budget