Scenario: Retiming Debate: Inputs & Outputs

Inputs and outputs contract

Inputs & Outputs for Scenario: Retiming Debate focuses on frequency target miss versus latency and verification budget. The goal is to connect observed QoR movement to mechanism, ownership, and regression risk.

Synthesis closure fails when teams optimize against different assumptions. Treat these artifacts as a signed handoff contract.

INPUTS
  - RTL tag and compile switches
  - SDC / policy constraints
  - Library and operating views
  - Optional physical estimates (topo/congestion)

OUTPUTS
  - QoR timing/area/power reports
  - transform/mapping summaries
  - owner-tagged closure memo
  - regression matrix verdict

Flow sequence

SYNTHESIS FLOW — Scenario: Retiming Debate

RTL + constraints
      |
      v
elaboration + checks
      |
      v
mapping + optimization
      |
      v
QoR reports (timing/area/power)
      |
      v
incremental ECO + regression

Primary metric: frequency target miss versus latency and verification budget

Ownership map

OWNERSHIP MAP — Scenario: Retiming Debate

artifact              owner
----------------      -----------------
compile owner       microarchitecture owner
timing/power owner  synthesis owner
cross-team review   formal owner

Every QoR movement needs a named owner before ECO.

Synthesis deep dive

Interview readiness comes from repeatable QoR reasoning under pressure.

Concept diagram

INTERVIEW ANSWER SHAPE

context -> metric -> mechanism -> fix -> regression -> ownership

Metric graph

PANEL SCORING

clarity      ███████
mechanism    ██████
regression   █████

Reports and artifacts

• mock scorecard

• scenario debrief

• Q&A coverage

• framework adherence

Mini case study

Candidate improved by replacing tool-command answers with evidence-driven closure narratives.

Debug branches

• State assumptions first

• Defend option tradeoffs

• Close with rollback/regression

Senior review question

Ask: what evidence proves this QoR move is real and stable?

Key takeaways

• State exact run context (RTL, SDC, libs, switches) with every QoR claim.

• Re-run timing, area, and power regressions after each synthesis ECO.

Common pitfalls

• Comparing runs with mismatched constraints or library views.

• Timing-only fixes that violate power or area budgets.

• Skipping equivalence checks after structural changes.

Principal synthesis review addendum

Retiming debate evaluates whether register movement is safer than RTL pipeline edits under schedule and formal constraints.

Metric: frequency target miss versus latency and verification budget