Scenario: Retiming Debate: Worked Example

Worked example

Worked Example for Scenario: Retiming Debate focuses on frequency target miss versus latency and verification budget. The goal is to connect observed QoR movement to mechanism, ownership, and regression risk.

A weekly compile reports frequency target miss versus latency and verification budget regression. Instead of random knob tuning, start by proving whether input context changed and which mechanism dominates.

Sequence under inspection

SYNTHESIS FLOW — Scenario: Retiming Debate

RTL + constraints
      |
      v
elaboration + checks
      |
      v
mapping + optimization
      |
      v
QoR reports (timing/area/power)
      |
      v
incremental ECO + regression

Primary metric: frequency target miss versus latency and verification budget

Retiming debate matrix

retime now?
benefit: Fmax
cost: formal + latency + schedule
decision by risk budget

1. Capture baseline and regressed artifact pair.

2. Confirm manifest parity (RTL, SDC, libs, switches).

3. Pin first metric drift and mechanism hypothesis.

4. Reproduce with retiming option sheet, equivalence plan, risk matrix.

5. Apply one reversible fix and run matrix regression.

Did the fix hold?

BEFORE / AFTER QOR — Scenario: Retiming Debate

QoR score
  0 |                     --- target zone
 -1 |        ● regression
 -2 |             ● baseline
 -0.5|                  ● after fix
    +----------------------------------> iteration

Validate timing + area + power, not one number.

Synthesis deep dive

Interview readiness comes from repeatable QoR reasoning under pressure.

Concept diagram

INTERVIEW ANSWER SHAPE

context -> metric -> mechanism -> fix -> regression -> ownership

Metric graph

PANEL SCORING

clarity      ███████
mechanism    ██████
regression   █████

Reports and artifacts

• mock scorecard

• scenario debrief

• Q&A coverage

• framework adherence

Mini case study

Candidate improved by replacing tool-command answers with evidence-driven closure narratives.

Debug branches

• State assumptions first

• Defend option tradeoffs

• Close with rollback/regression

Senior review question

Ask: what evidence proves this QoR move is real and stable?

Key takeaways

• State exact run context (RTL, SDC, libs, switches) with every QoR claim.

• Re-run timing, area, and power regressions after each synthesis ECO.

Common pitfalls

• Comparing runs with mismatched constraints or library views.

• Timing-only fixes that violate power or area budgets.

• Skipping equivalence checks after structural changes.

Principal synthesis review addendum

Retiming debate evaluates whether register movement is safer than RTL pipeline edits under schedule and formal constraints.

Metric: frequency target miss versus latency and verification budget