Structuring & Buffering: Review Checklist

Review checklist

Review Checklist for Structuring & Buffering focuses on logic depth, fanout violations, buffer count, slew violations. The goal is to connect observed QoR movement to mechanism, ownership, and regression risk.

• Run manifest is attached (RTL/SDC/libs/switches).

• Primary metric and impacted lane are named.

• Mechanism hypothesis is evidence-backed.

• Fix is reversible and owner-assigned.

• Regression matrix includes timing, area, power, and equivalence as needed.

• Owners signed: synthesis owner, PD owner, STA owner.

Sign-off ownership

OWNERSHIP MAP — Structuring & Buffering

artifact              owner
----------------      -----------------
compile owner       synthesis owner
timing/power owner  PD owner
cross-team review   STA owner

Every QoR movement needs a named owner before ECO.

Synthesis deep dive

Mapping converts logic intent into real PPA outcomes.

Concept diagram

MAPPING LOOP

boolean net -> library mapping -> optimization -> report and iterate

Metric graph

MAPPING IMPACT

depth reduction   ███████
fanout cleanup    █████
runtime overhead  ███

Reports and artifacts

• mapping summary

• critical path cell list

• fanout/slew report

• library coverage

Mini case study

Cell-heavy critical path improved after restructuring, while blanket buffering had worsened power.

Debug branches

• Depth issue -> structure

• Fanout issue -> buffers

• Library mismatch -> view audit

Senior review question

Ask: what evidence proves this QoR move is real and stable?

Key takeaways

• State exact run context (RTL, SDC, libs, switches) with every QoR claim.

• Re-run timing, area, and power regressions after each synthesis ECO.

Common pitfalls

• Comparing runs with mismatched constraints or library views.

• Timing-only fixes that violate power or area budgets.

• Skipping equivalence checks after structural changes.

Principal synthesis review addendum

Structuring rewrites logic cones and buffering controls transition/fanout; both directly affect timing, area, and power in different corners.

Metric: logic depth, fanout violations, buffer count, slew violations