Technology Mapping

What this topic teaches

Technology Mapping teaches how to turn synthesis intent into stable QoR outcomes. Boolean network mapping selects implementation cells from libraries; mapping choices shape depth, transition behavior, and downstream routability. Senior practice is proving whether metric movement is real, reproducible, and owned.

The senior-engineer question

When mapped cell count, path delay after mapping, library coverage gaps moves, can you name the run context, mechanism, owner, and minimal fix that holds under regression?

SYNTHESIS FLOW — Technology Mapping

RTL + constraints
      |
      v
elaboration + checks
      |
      v
mapping + optimization
      |
      v
QoR reports (timing/area/power)
      |
      v
incremental ECO + regression

Primary metric: mapped cell count, path delay after mapping, library coverage gaps

Picture the synthesis flow

Draw the behavior before diving into tool commands. These diagrams are the whiteboard models to memorize for reviews and interviews.

Mapping from Boolean to cells

BOOLEAN NETWORK
  -> cut enumeration
  -> library match
  -> delay/area costing
  -> mapped netlist

QoR trend shape

QOR TREND — Technology Mapping

metric quality
  ^
  |                      target band
  |                o  o  o
  |            o
  |      o  regression
  +----------------------------------> synthesis iteration
   baseline    tuning     signoff-ready

Track: mapped cell count, path delay after mapping, library coverage gaps

Who owns which layer

SYNTHESIS OWNERSHIP LAYERS — Technology Mapping

layer               owns                          failure mode
----------------    ---------------------------   -------------------------
constraints         clocks/exceptions/policy      fake QoR optimism
mapping             cell choices/structure        depth/fanout regressions
optimization        timing/power tradeoffs        one-metric overfitting
physical-aware      topo/congestion estimates     handoff delta surprises
closure             ECO order/regression          fixes break other corners

Evidence to collect

• Primary metric: mapped cell count, path delay after mapping, library coverage gaps.

• Primary artifact: mapping report, unmapped logic log, critical path cell list.

• Owners to involve: synthesis owner, library owner, STA owner.

• One baseline run and one regressed run with matching manifests.

• A rollback-safe change proposal with full regression scope.

Ownership map

OWNERSHIP MAP — Technology Mapping

artifact              owner
----------------      -----------------
compile owner       synthesis owner
timing/power owner  library owner
cross-team review   STA owner

Every QoR movement needs a named owner before ECO.

Subpages in this topic

Each topic is taught through mechanism, interfaces, reports, debug, worked example, pitfalls, interview, checklist, theory, design space, expanded case study, walkthrough, comparison matrix, software view, and silicon PPA impact.

Key takeaways

• Always present QoR with run context and artifact.

• Prefer reversible fixes with explicit rollback criteria.

• Re-run timing, area, and power checks before closing.

Common pitfalls

• Comparing unlike compile contexts.

• Timing-only wins that worsen power or area.

• Skipping equivalence checks after structural changes.

Synthesis deep dive

Mapping converts logic intent into real PPA outcomes.

Concept diagram

MAPPING LOOP

boolean net -> library mapping -> optimization -> report and iterate

Metric graph

MAPPING IMPACT

depth reduction   ███████
fanout cleanup    █████
runtime overhead  ███

Reports and artifacts

• mapping summary

• critical path cell list

• fanout/slew report

• library coverage

Mini case study

Cell-heavy critical path improved after restructuring, while blanket buffering had worsened power.

Debug branches

• Depth issue -> structure

• Fanout issue -> buffers

• Library mismatch -> view audit

Senior review question

Ask: what evidence proves this QoR move is real and stable?

Key takeaways

• State exact run context (RTL, SDC, libs, switches) with every QoR claim.

• Re-run timing, area, and power regressions after each synthesis ECO.

Common pitfalls

• Comparing runs with mismatched constraints or library views.

• Timing-only fixes that violate power or area budgets.

• Skipping equivalence checks after structural changes.