Synthesis & Logic Optimization · All levels

Technology Mapping: Review Checklist

Review Checklist for Technology Mapping.

Review checklist

Review Checklist for Technology Mapping focuses on mapped cell count, path delay after mapping, library coverage gaps. The goal is to connect observed QoR movement to mechanism, ownership, and regression risk.

  • Run manifest is attached (RTL/SDC/libs/switches).

  • Primary metric and impacted lane are named.

  • Mechanism hypothesis is evidence-backed.

  • Fix is reversible and owner-assigned.

  • Regression matrix includes timing, area, power, and equivalence as needed.

  • Owners signed: synthesis owner, library owner, STA owner.

Sign-off ownership

diagram
OWNERSHIP MAP — Technology Mapping

artifact              owner
----------------      -----------------
compile owner       synthesis owner
timing/power owner  library owner
cross-team review   STA owner

Every QoR movement needs a named owner before ECO.

Synthesis deep dive

Mapping converts logic intent into real PPA outcomes.

Concept diagram

diagram
MAPPING LOOP

boolean net -> library mapping -> optimization -> report and iterate

Metric graph

diagram
MAPPING IMPACT

depth reduction   ███████
fanout cleanup    █████
runtime overhead  ███

Reports and artifacts

  • mapping summary

  • critical path cell list

  • fanout/slew report

  • library coverage

Mini case study

Cell-heavy critical path improved after restructuring, while blanket buffering had worsened power.

Debug branches

  • Depth issue -> structure

  • Fanout issue -> buffers

  • Library mismatch -> view audit

Senior review question

Ask: what evidence proves this QoR move is real and stable?

Key takeaways

  • State exact run context (RTL, SDC, libs, switches) with every QoR claim.

  • Re-run timing, area, and power regressions after each synthesis ECO.

Common pitfalls

  • Comparing runs with mismatched constraints or library views.

  • Timing-only fixes that violate power or area budgets.

  • Skipping equivalence checks after structural changes.

Principal synthesis review addendum

Boolean network mapping selects implementation cells from libraries; mapping choices shape depth, transition behavior, and downstream routability.

Metric: mapped cell count, path delay after mapping, library coverage gaps