Technology Mapping: Debug Playbook

Debug playbook

Debug Playbook for Technology Mapping focuses on mapped cell count, path delay after mapping, library coverage gaps. The goal is to connect observed QoR movement to mechanism, ownership, and regression risk.

Synthesis debug finds the first causal drift, not the loudest downstream symptom.

Root-cause tree

ROOT-CAUSE TREE — Technology Mapping

mapped cell count, path delay after mapping, library coverage gaps regressed
        |
   same RTL/constraints tag?
     /              \
   no                yes
   |                  |
input drift      transform side-effect
 /    \             /         \
SDC    libs      mapping      physical estimate
diff   diff      choice       mismatch

1. Freeze baseline and regressed run manifests.

2. Verify RTL/SDC/library deltas before transform tuning.

3. Classify issue: constraints, mapping choice, physical estimate, or ECO side effect.

4. Pick one minimal reversible change.

5. Re-run full timing/area/power checks with ownership signoff.

Review memo template

STAFF SYNTHESIS REVIEW MEMO — Mapping & Optimization / Technology Mapping

1. Symptom
   - Watched metric: mapped cell count, path delay after mapping, library coverage gaps
   - Affected compile run: <tag/build ID>
   - Impacted path/class: <critical group / power lane / area lane>
   - Database tags: <RTL, SDC, libs, switches>

2. Mechanism hypothesis
   - Primary mechanism: Boolean network mapping selects implementation cells from libraries; mapping choices shape depth, transition behavior, and downstream routability.
   - Competing hypothesis: <constraint drift, mapping choice, physical estimate mismatch>
   - Missing evidence: <report diff, dashboard trend, ownership board>

3. Proposed action
   - Minimal reversible change: <constraint patch, compile knob, ECO cell move>
   - Expected movement: <timing / area / power delta>
   - Regression risk: hold, power spike, leakage drift, formal mismatch

4. Signoff
   - Re-run artifact: mapping report, unmapped logic log, critical path cell list
   - Required owners: synthesis owner, library owner, STA owner
   - Final decision: merge, rollback, or escalate

Synthesis deep dive

Mapping converts logic intent into real PPA outcomes.

Concept diagram

MAPPING LOOP

boolean net -> library mapping -> optimization -> report and iterate

Metric graph

MAPPING IMPACT

depth reduction   ███████
fanout cleanup    █████
runtime overhead  ███

Reports and artifacts

• mapping summary

• critical path cell list

• fanout/slew report

• library coverage

Mini case study

Cell-heavy critical path improved after restructuring, while blanket buffering had worsened power.

Debug branches

• Depth issue -> structure

• Fanout issue -> buffers

• Library mismatch -> view audit

Senior review question

Ask: what evidence proves this QoR move is real and stable?

Key takeaways

• State exact run context (RTL, SDC, libs, switches) with every QoR claim.

• Re-run timing, area, and power regressions after each synthesis ECO.

Common pitfalls

• Comparing runs with mismatched constraints or library views.

• Timing-only fixes that violate power or area budgets.

• Skipping equivalence checks after structural changes.

Principal synthesis review addendum

Boolean network mapping selects implementation cells from libraries; mapping choices shape depth, transition behavior, and downstream routability.

Metric: mapped cell count, path delay after mapping, library coverage gaps