Technology Mapping: Interview Drills

Interview drills

Interview Drills for Technology Mapping focuses on mapped cell count, path delay after mapping, library coverage gaps. The goal is to connect observed QoR movement to mechanism, ownership, and regression risk.

PROMPT
You observe mapped cell count, path delay after mapping, library coverage gaps in Technology Mapping. Walk through root cause and closure plan.

STRONG ANSWER
1. Names run context and affected QoR lane.
2. Explains Boolean network mapping selects implementation cells from libraries; mapping choices shape depth, transition behavior, and downstream routability.
3. Requests mapping report, unmapped logic log, critical path cell list.
4. Proposes one reversible fix and full regression scope.

WEAK ANSWER
Jumps to random tool switches without mechanism evidence.

Whiteboard diagram

Mapping from Boolean to cells

BOOLEAN NETWORK
  -> cut enumeration
  -> library match
  -> delay/area costing
  -> mapped netlist

Root-cause narration

ROOT-CAUSE TREE — Technology Mapping

mapped cell count, path delay after mapping, library coverage gaps regressed
        |
   same RTL/constraints tag?
     /              \
   no                yes
   |                  |
input drift      transform side-effect
 /    \             /         \
SDC    libs      mapping      physical estimate
diff   diff      choice       mismatch

Synthesis deep dive

Mapping converts logic intent into real PPA outcomes.

Concept diagram

MAPPING LOOP

boolean net -> library mapping -> optimization -> report and iterate

Metric graph

MAPPING IMPACT

depth reduction   ███████
fanout cleanup    █████
runtime overhead  ███

Reports and artifacts

• mapping summary

• critical path cell list

• fanout/slew report

• library coverage

Mini case study

Cell-heavy critical path improved after restructuring, while blanket buffering had worsened power.

Debug branches

• Depth issue -> structure

• Fanout issue -> buffers

• Library mismatch -> view audit

Senior review question

Ask: what evidence proves this QoR move is real and stable?

Key takeaways

• State exact run context (RTL, SDC, libs, switches) with every QoR claim.

• Re-run timing, area, and power regressions after each synthesis ECO.

Common pitfalls

• Comparing runs with mismatched constraints or library views.

• Timing-only fixes that violate power or area budgets.

• Skipping equivalence checks after structural changes.

Principal synthesis review addendum

Boolean network mapping selects implementation cells from libraries; mapping choices shape depth, transition behavior, and downstream routability.

Metric: mapped cell count, path delay after mapping, library coverage gaps