Synthesis & Logic Optimization · All levels

Timing-Driven Synthesis

Mapping & Optimization: Timing-driven compile focuses optimization where slack is most constrained, balancing global QoR instead of over-optimizing non-critical logic.

What this topic teaches

Timing-Driven Synthesis teaches how to turn synthesis intent into stable QoR outcomes. Timing-driven compile focuses optimization where slack is most constrained, balancing global QoR instead of over-optimizing non-critical logic. Senior practice is proving whether metric movement is real, reproducible, and owned.

The senior-engineer question

When critical path WNS, violating endpoint count, compile effort distribution moves, can you name the run context, mechanism, owner, and minimal fix that holds under regression?

diagram

SYNTHESIS FLOW — Timing-Driven Synthesis

RTL + constraints
      |
      v
elaboration + checks
      |
      v
mapping + optimization
      |
      v
QoR reports (timing/area/power)
      |
      v
incremental ECO + regression

Primary metric: critical path WNS, violating endpoint count, compile effort distribution

Picture the synthesis flow

Draw the behavior before diving into tool commands. These diagrams are the whiteboard models to memorize for reviews and interviews.

Timing-driven effort allocation

diagram

path groups ranked by slack
      |
      v
high effort on critical groups
medium effort on near-critical
low effort elsewhere

QoR trend shape

diagram

QOR TREND — Timing-Driven Synthesis

metric quality
  ^
  |                      target band
  |                o  o  o
  |            o
  |      o  regression
  +----------------------------------> synthesis iteration
   baseline    tuning     signoff-ready

Track: critical path WNS, violating endpoint count, compile effort distribution

Who owns which layer

diagram

SYNTHESIS OWNERSHIP LAYERS — Timing-Driven Synthesis

layer               owns                          failure mode
----------------    ---------------------------   -------------------------
constraints         clocks/exceptions/policy      fake QoR optimism
mapping             cell choices/structure        depth/fanout regressions
optimization        timing/power tradeoffs        one-metric overfitting
physical-aware      topo/congestion estimates     handoff delta surprises
closure             ECO order/regression          fixes break other corners

Evidence to collect

Primary metric: critical path WNS, violating endpoint count, compile effort distribution.
Primary artifact: critical range report, path-group WNS report, effort histogram.
Owners to involve: synthesis lead, STA owner.
One baseline run and one regressed run with matching manifests.
A rollback-safe change proposal with full regression scope.

Ownership map

diagram

OWNERSHIP MAP — Timing-Driven Synthesis

artifact              owner
----------------      -----------------
compile owner       synthesis lead
timing/power owner  STA owner

Every QoR movement needs a named owner before ECO.

Subpages in this topic

Each topic is taught through mechanism, interfaces, reports, debug, worked example, pitfalls, interview, checklist, theory, design space, expanded case study, walkthrough, comparison matrix, software view, and silicon PPA impact.

Key takeaways

Always present QoR with run context and artifact.
Prefer reversible fixes with explicit rollback criteria.
Re-run timing, area, and power checks before closing.

Common pitfalls

Comparing unlike compile contexts.
Timing-only wins that worsen power or area.
Skipping equivalence checks after structural changes.

Synthesis deep dive

Mapping converts logic intent into real PPA outcomes.

Concept diagram

diagram

MAPPING LOOP

boolean net -> library mapping -> optimization -> report and iterate

Metric graph

diagram

MAPPING IMPACT

depth reduction   ███████
fanout cleanup    █████
runtime overhead  ███

Reports and artifacts

mapping summary
critical path cell list
fanout/slew report
library coverage

Mini case study

Cell-heavy critical path improved after restructuring, while blanket buffering had worsened power.

Debug branches

Depth issue -> structure
Fanout issue -> buffers
Library mismatch -> view audit

Senior review question

Ask: what evidence proves this QoR move is real and stable?

Key takeaways

State exact run context (RTL, SDC, libs, switches) with every QoR claim.
Re-run timing, area, and power regressions after each synthesis ECO.

Common pitfalls

Comparing runs with mismatched constraints or library views.
Timing-only fixes that violate power or area budgets.
Skipping equivalence checks after structural changes.

Practice this lesson