Synthesis & Logic Optimization · All levels
Timing-Driven Synthesis: Comparison Matrix
Comparison Matrix for Timing-Driven Synthesis.
Comparison matrix
Optimization levers differ by dominant bottleneck: depth, fanout, or library fit.
+------------------+----------------+----------------+----------------+
| Approach | Strength | Weakness | Best when |
+------------------+----------------+----------------+----------------+
| Conservative | stable | slower | new design spin |
| Balanced | practical | needs monitoring | normal closure |
| Aggressive | fast | higher risk | schedule crunch |
| Structural | durable | long loop | repeat offender |
+------------------+----------------+----------------+----------------+When to choose each approach
Select strategy by risk budget, not convenience.
Interview traps
Skipping manifest diff
No side-effect regression
Evidence comparison
SYNTHESIS EVIDENCE MATRIX — Timing-Driven Synthesis
+--------------------+------------------------+--------------------------+-------------------------+
| Evidence | Tells you | Does not prove | Next action |
+--------------------+------------------------+--------------------------+-------------------------+
| compile QoR report | metric movement | root-cause class | inspect transform logs |
| SDC diff | constraint drift | library quality | rerun with baseline SDC |
| library map diff | cell view changes | RTL intent quality | lock/validate lib set |
| topo vs logical QoR | physical correlation | final route signoff | PD trial correlation |
| regression matrix | closure stability | architecture optimality | decide merge/rollback |
+--------------------+------------------------+--------------------------+-------------------------+Synthesis deep dive
Mapping converts logic intent into real PPA outcomes.
Concept diagram
MAPPING LOOP
boolean net -> library mapping -> optimization -> report and iterateMetric graph
MAPPING IMPACT
depth reduction ███████
fanout cleanup █████
runtime overhead ███Reports and artifacts
mapping summary
critical path cell list
fanout/slew report
library coverage
Mini case study
Cell-heavy critical path improved after restructuring, while blanket buffering had worsened power.
Debug branches
Depth issue -> structure
Fanout issue -> buffers
Library mismatch -> view audit
Senior review question
Ask: what evidence proves this QoR move is real and stable?
Key takeaways
State exact run context (RTL, SDC, libs, switches) with every QoR claim.
Re-run timing, area, and power regressions after each synthesis ECO.
Common pitfalls
Comparing runs with mismatched constraints or library views.
Timing-only fixes that violate power or area budgets.
Skipping equivalence checks after structural changes.
Principal synthesis review addendum
Timing-driven compile focuses optimization where slack is most constrained, balancing global QoR instead of over-optimizing non-critical logic.
Metric: critical path WNS, violating endpoint count, compile effort distribution