Synthesis & Logic Optimization · All levels

Timing-Driven Synthesis: Design Space

Design Space for Timing-Driven Synthesis.

Design space exploration

For Timing-Driven Synthesis, options trade QoR gain, risk, and schedule.

Option A — conservative

Conservative constraints: helps predictability
Risk: slower PPA gains
Validate with: first-silicon safety

Option B — balanced

Balanced QoR tuning: helps stable closure
Risk: requires discipline
Validate with: typical product mode

Option C — aggressive compile

Aggressive compile push: helps fast timing recovery
Risk: power/hold regressions
Validate with: late schedule

Option D — structural change

Structural RTL change: helps long-term fix
Risk: schedule impact
Validate with: recurring bottleneck

diagram

DESIGN SPACE — Timing-Driven Synthesis
QoR gain <-> regression risk <-> schedule pressure

Design pitfalls

Single-metric optimization
No rollback path
Weak run comparability

Tradeoff curve

diagram

BEFORE / AFTER QOR — Timing-Driven Synthesis

QoR score
  0 |                     --- target zone
 -1 |        ● regression
 -2 |             ● baseline
 -0.5|                  ● after fix
    +----------------------------------> iteration

Validate timing + area + power, not one number.

Synthesis deep dive

Mapping converts logic intent into real PPA outcomes.

Concept diagram

diagram

MAPPING LOOP

boolean net -> library mapping -> optimization -> report and iterate

Metric graph

diagram

MAPPING IMPACT

depth reduction   ███████
fanout cleanup    █████
runtime overhead  ███

Reports and artifacts

mapping summary
critical path cell list
fanout/slew report
library coverage

Mini case study

Cell-heavy critical path improved after restructuring, while blanket buffering had worsened power.

Debug branches

Depth issue -> structure
Fanout issue -> buffers
Library mismatch -> view audit

Senior review question

Ask: what evidence proves this QoR move is real and stable?

Key takeaways

State exact run context (RTL, SDC, libs, switches) with every QoR claim.
Re-run timing, area, and power regressions after each synthesis ECO.

Common pitfalls

Comparing runs with mismatched constraints or library views.
Timing-only fixes that violate power or area budgets.
Skipping equivalence checks after structural changes.

Principal synthesis review addendum

Timing-driven compile focuses optimization where slack is most constrained, balancing global QoR instead of over-optimizing non-critical logic.

Metric: critical path WNS, violating endpoint count, compile effort distribution

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