Synthesis & Logic Optimization · All levels

Physical-Aware Debug

Physical-Aware Synthesis: Physical-aware debug classifies QoR regressions into modeling error, placement pressure, or true logic issues before ECO churn starts.

What this topic teaches

Physical-Aware Debug teaches how to turn synthesis intent into stable QoR outcomes. Physical-aware debug classifies QoR regressions into modeling error, placement pressure, or true logic issues before ECO churn starts. Senior practice is proving whether metric movement is real, reproducible, and owned.

The senior-engineer question

When logic-vs-physical delta isolation time, root-cause class distribution moves, can you name the run context, mechanism, owner, and minimal fix that holds under regression?

diagram

SYNTHESIS FLOW — Physical-Aware Debug

RTL + constraints
      |
      v
elaboration + checks
      |
      v
mapping + optimization
      |
      v
QoR reports (timing/area/power)
      |
      v
incremental ECO + regression

Primary metric: logic-vs-physical delta isolation time, root-cause class distribution

Picture the synthesis flow

Draw the behavior before diving into tool commands. These diagrams are the whiteboard models to memorize for reviews and interviews.

Logic vs physical delta

diagram

compile QoR good, route QoR bad?
  -> model mismatch
  -> congestion issue
  -> true logic bottleneck

QoR trend shape

diagram

QOR TREND — Physical-Aware Debug

metric quality
  ^
  |                      target band
  |                o  o  o
  |            o
  |      o  regression
  +----------------------------------> synthesis iteration
   baseline    tuning     signoff-ready

Track: logic-vs-physical delta isolation time, root-cause class distribution

Who owns which layer

diagram

SYNTHESIS OWNERSHIP LAYERS — Physical-Aware Debug

layer               owns                          failure mode
----------------    ---------------------------   -------------------------
constraints         clocks/exceptions/policy      fake QoR optimism
mapping             cell choices/structure        depth/fanout regressions
optimization        timing/power tradeoffs        one-metric overfitting
physical-aware      topo/congestion estimates     handoff delta surprises
closure             ECO order/regression          fixes break other corners

Evidence to collect

Primary metric: logic-vs-physical delta isolation time, root-cause class distribution.
Primary artifact: delta-debug checklist, topo/route compare, ownership board.
Owners to involve: synthesis owner, PD owner, STA owner.
One baseline run and one regressed run with matching manifests.
A rollback-safe change proposal with full regression scope.

Ownership map

diagram

OWNERSHIP MAP — Physical-Aware Debug

artifact              owner
----------------      -----------------
compile owner       synthesis owner
timing/power owner  PD owner
cross-team review   STA owner

Every QoR movement needs a named owner before ECO.

Subpages in this topic

Each topic is taught through mechanism, interfaces, reports, debug, worked example, pitfalls, interview, checklist, theory, design space, expanded case study, walkthrough, comparison matrix, software view, and silicon PPA impact.

Key takeaways

Always present QoR with run context and artifact.
Prefer reversible fixes with explicit rollback criteria.
Re-run timing, area, and power checks before closing.

Common pitfalls

Comparing unlike compile contexts.
Timing-only wins that worsen power or area.
Skipping equivalence checks after structural changes.

Synthesis deep dive

Physical-aware synthesis reduces logic-to-route surprise when correlation is monitored.

Concept diagram

diagram

PHYSICAL-AWARE LOOP

topo compile -> congestion hints -> handoff -> PD correlation

Metric graph

diagram

CORRELATION DELTA

logic view WNS      ███████
topo view WNS       █████
route trial WNS     ████

Reports and artifacts

topo QoR
congestion heatmap
handoff manifest
delta compare vs PD

Mini case study

Topo compile looked clean, but hotspot congestion predicted route failure and prevented late ECO churn.

Debug branches

Check hotspot ownership
Bound correlation drift
Escalate if handoff assumptions stale

Senior review question

Ask: what evidence proves this QoR move is real and stable?

Key takeaways

State exact run context (RTL, SDC, libs, switches) with every QoR claim.
Re-run timing, area, and power regressions after each synthesis ECO.

Common pitfalls

Comparing runs with mismatched constraints or library views.
Timing-only fixes that violate power or area budgets.
Skipping equivalence checks after structural changes.

Practice this lesson