Physical-Aware Debug: Interview Drills

Interview drills

Interview Drills for Physical-Aware Debug focuses on logic-vs-physical delta isolation time, root-cause class distribution. The goal is to connect observed QoR movement to mechanism, ownership, and regression risk.

PROMPT
You observe logic-vs-physical delta isolation time, root-cause class distribution in Physical-Aware Debug. Walk through root cause and closure plan.

STRONG ANSWER
1. Names run context and affected QoR lane.
2. Explains Physical-aware debug classifies QoR regressions into modeling error, placement pressure, or true logic issues before ECO churn starts.
3. Requests delta-debug checklist, topo/route compare, ownership board.
4. Proposes one reversible fix and full regression scope.

WEAK ANSWER
Jumps to random tool switches without mechanism evidence.

Whiteboard diagram

Logic vs physical delta

compile QoR good, route QoR bad?
  -> model mismatch
  -> congestion issue
  -> true logic bottleneck

Root-cause narration

ROOT-CAUSE TREE — Physical-Aware Debug

logic-vs-physical delta isolation time, root-cause class distribution regressed
        |
   same RTL/constraints tag?
     /              \
   no                yes
   |                  |
input drift      transform side-effect
 /    \             /         \
SDC    libs      mapping      physical estimate
diff   diff      choice       mismatch

Synthesis deep dive

Physical-aware synthesis reduces logic-to-route surprise when correlation is monitored.

Concept diagram

PHYSICAL-AWARE LOOP

topo compile -> congestion hints -> handoff -> PD correlation

Metric graph

CORRELATION DELTA

logic view WNS      ███████
topo view WNS       █████
route trial WNS     ████

Reports and artifacts

• topo QoR

• congestion heatmap

• handoff manifest

• delta compare vs PD

Mini case study

Topo compile looked clean, but hotspot congestion predicted route failure and prevented late ECO churn.

Debug branches

• Check hotspot ownership

• Bound correlation drift

• Escalate if handoff assumptions stale

Senior review question

Ask: what evidence proves this QoR move is real and stable?

Key takeaways

• State exact run context (RTL, SDC, libs, switches) with every QoR claim.

• Re-run timing, area, and power regressions after each synthesis ECO.

Common pitfalls

• Comparing runs with mismatched constraints or library views.

• Timing-only fixes that violate power or area budgets.

• Skipping equivalence checks after structural changes.

Principal synthesis review addendum

Physical-aware debug classifies QoR regressions into modeling error, placement pressure, or true logic issues before ECO churn starts.

Metric: logic-vs-physical delta isolation time, root-cause class distribution