Synthesis & Logic Optimization · All levels
Physical-Aware Debug: Mechanism
Mechanism for Physical-Aware Debug.
Mechanism to understand
Mechanism for Physical-Aware Debug focuses on logic-vs-physical delta isolation time, root-cause class distribution. The goal is to connect observed QoR movement to mechanism, ownership, and regression risk.
Physical-aware debug classifies QoR regressions into modeling error, placement pressure, or true logic issues before ECO churn starts. Treat synthesis as a contract: constraints + transforms + reports must agree.
Identify which lane moved first: timing, area, power, or runtime.
Identify whether drift is input, transform, or correlation related.
Identify owner before applying any ECO.
Flow model
SYNTHESIS FLOW — Physical-Aware Debug
RTL + constraints
|
v
elaboration + checks
|
v
mapping + optimization
|
v
QoR reports (timing/area/power)
|
v
incremental ECO + regression
Primary metric: logic-vs-physical delta isolation time, root-cause class distributionLogic vs physical delta
compile QoR good, route QoR bad?
-> model mismatch
-> congestion issue
-> true logic bottleneckLayer responsibilities
SYNTHESIS OWNERSHIP LAYERS — Physical-Aware Debug
layer owns failure mode
---------------- --------------------------- -------------------------
constraints clocks/exceptions/policy fake QoR optimism
mapping cell choices/structure depth/fanout regressions
optimization timing/power tradeoffs one-metric overfitting
physical-aware topo/congestion estimates handoff delta surprises
closure ECO order/regression fixes break other cornersSynthesis deep dive
Physical-aware synthesis reduces logic-to-route surprise when correlation is monitored.
Concept diagram
PHYSICAL-AWARE LOOP
topo compile -> congestion hints -> handoff -> PD correlationMetric graph
CORRELATION DELTA
logic view WNS ███████
topo view WNS █████
route trial WNS ████Reports and artifacts
topo QoR
congestion heatmap
handoff manifest
delta compare vs PD
Mini case study
Topo compile looked clean, but hotspot congestion predicted route failure and prevented late ECO churn.
Debug branches
Check hotspot ownership
Bound correlation drift
Escalate if handoff assumptions stale
Senior review question
Ask: what evidence proves this QoR move is real and stable?
Key takeaways
State exact run context (RTL, SDC, libs, switches) with every QoR claim.
Re-run timing, area, and power regressions after each synthesis ECO.
Common pitfalls
Comparing runs with mismatched constraints or library views.
Timing-only fixes that violate power or area budgets.
Skipping equivalence checks after structural changes.
Mechanism deep dive
Physical-aware debug classifies QoR regressions into modeling error, placement pressure, or true logic issues before ECO churn starts.