Physical-Aware Debug: Pitfalls & Red Flags

Pitfalls and red flags

Pitfalls & Red Flags for Physical-Aware Debug focuses on logic-vs-physical delta isolation time, root-cause class distribution. The goal is to connect observed QoR movement to mechanism, ownership, and regression risk.

• Dashboard trend breaks without recorded manifest changes.

• dont_touch list grows without periodic removal review.

• Retiming gains claimed without formal evidence.

• Topographical numbers treated as final signoff.

• Fix improves one lane but silently regresses another.

Layer responsibility check

SYNTHESIS OWNERSHIP LAYERS — Physical-Aware Debug

layer               owns                          failure mode
----------------    ---------------------------   -------------------------
constraints         clocks/exceptions/policy      fake QoR optimism
mapping             cell choices/structure        depth/fanout regressions
optimization        timing/power tradeoffs        one-metric overfitting
physical-aware      topo/congestion estimates     handoff delta surprises
closure             ECO order/regression          fixes break other corners

Synthesis deep dive

Physical-aware synthesis reduces logic-to-route surprise when correlation is monitored.

Concept diagram

PHYSICAL-AWARE LOOP

topo compile -> congestion hints -> handoff -> PD correlation

Metric graph

CORRELATION DELTA

logic view WNS      ███████
topo view WNS       █████
route trial WNS     ████

Reports and artifacts

• topo QoR

• congestion heatmap

• handoff manifest

• delta compare vs PD

Mini case study

Topo compile looked clean, but hotspot congestion predicted route failure and prevented late ECO churn.

Debug branches

• Check hotspot ownership

• Bound correlation drift

• Escalate if handoff assumptions stale

Senior review question

Ask: what evidence proves this QoR move is real and stable?

Key takeaways

• State exact run context (RTL, SDC, libs, switches) with every QoR claim.

• Re-run timing, area, and power regressions after each synthesis ECO.

Common pitfalls

• Comparing runs with mismatched constraints or library views.

• Timing-only fixes that violate power or area budgets.

• Skipping equivalence checks after structural changes.

Principal synthesis review addendum

Physical-aware debug classifies QoR regressions into modeling error, placement pressure, or true logic issues before ECO churn starts.

Metric: logic-vs-physical delta isolation time, root-cause class distribution