Synthesis & Logic Optimization · All levels

Physical-Aware Debug: Step-by-Step Walkthrough

Step-by-Step Walkthrough for Physical-Aware Debug.

Step-by-step analysis walkthrough

Use when you own Physical-Aware Debug in a synthesis closure review.

Confirm exact run context (RTL/SDC/lib/switch set).
Open section QoR dashboard and identify first drift.
Inspect topic-level report for mechanism evidence.
Determine owner and candidate reversible action.
Apply one change only; avoid bundled fixes.
Run full timing/area/power checks.
Validate side effects on neighboring path groups.
Publish memo with outcome and residual risk.

Artifacts to collect

delta-debug checklist, topo/route compare, ownership board
QoR dashboard
run manifest
constraint diff
regression matrix

Decision memo template

diagram

SYNTHESIS DECISION MEMO — Physical-Aware Debug
run context:
observed metric:
hypothesis:
fix:
regression:
owners: synthesis owner, PD owner, STA owner

Reference visuals

Logic vs physical delta

diagram

compile QoR good, route QoR bad?
  -> model mismatch
  -> congestion issue
  -> true logic bottleneck

Synthesis deep dive

Physical-aware synthesis reduces logic-to-route surprise when correlation is monitored.

Concept diagram

diagram

PHYSICAL-AWARE LOOP

topo compile -> congestion hints -> handoff -> PD correlation

Metric graph

diagram

CORRELATION DELTA

logic view WNS      ███████
topo view WNS       █████
route trial WNS     ████

Reports and artifacts

topo QoR
congestion heatmap
handoff manifest
delta compare vs PD

Mini case study

Topo compile looked clean, but hotspot congestion predicted route failure and prevented late ECO churn.

Debug branches

Check hotspot ownership
Bound correlation drift
Escalate if handoff assumptions stale

Senior review question

Ask: what evidence proves this QoR move is real and stable?

Key takeaways

State exact run context (RTL, SDC, libs, switches) with every QoR claim.
Re-run timing, area, and power regressions after each synthesis ECO.

Common pitfalls

Comparing runs with mismatched constraints or library views.
Timing-only fixes that violate power or area budgets.
Skipping equivalence checks after structural changes.

Principal synthesis review addendum

Physical-aware debug classifies QoR regressions into modeling error, placement pressure, or true logic issues before ECO churn starts.

Metric: logic-vs-physical delta isolation time, root-cause class distribution

Practice this lesson