Physical-Aware Debug: Theory Deep Dive

Foundational theory

Physical-Aware Debug is a core part of Physical-Aware Synthesis. Physical-aware debug classifies QoR regressions into modeling error, placement pressure, or true logic issues before ECO churn starts. Senior synthesis engineers connect every QoR claim to constraint context, compile setup, and reproducible artifacts.

Core concepts explained

• Physical-aware debug classifies QoR regressions into modeling error, placement pressure, or true logic issues before ECO churn starts.

• Primary metric: logic-vs-physical delta isolation time, root-cause class distribution

• Primary artifact: delta-debug checklist, topo/route compare, ownership board

• Owners: synthesis owner, PD owner, STA owner

• Compare timing, area, and power together

• Preserve run manifest for every regression jump

Why this matters at closure

At tapeout pace, Physical-Aware Debug decisions can either shorten closure loops or create hidden debt. Physical-aware synthesis improves predictability between logic and implementation views.

Mental model

compile QoR good, route QoR bad?
  -> model mismatch
  -> congestion issue
  -> true logic bottleneck

Worked intuition

1. Freeze RTL tag, constraint tag, and compile switches.

2. Open logic-vs-physical delta isolation time, root-cause class distribution and isolate the first meaningful regression.

3. Classify whether issue is constraints, mapping transform, or physical estimate.

4. Collect delta-debug checklist, topo/route compare, ownership board and owner signoff evidence.

5. Pick minimal reversible fix and define rollback criteria.

6. Run timing + power + area regression matrix before merge.

Common misconceptions

• Better WNS always means better overall QoR.

• dont_touch is harmless if timing still passes.

• Retiming gain is free and always safe for formal.

• Topographical estimates are equivalent to signoff route outcomes.

Visual reinforcement

Logic vs physical delta

compile QoR good, route QoR bad?
  -> model mismatch
  -> congestion issue
  -> true logic bottleneck

Layer responsibilities

SYNTHESIS OWNERSHIP LAYERS — Physical-Aware Debug

layer               owns                          failure mode
----------------    ---------------------------   -------------------------
constraints         clocks/exceptions/policy      fake QoR optimism
mapping             cell choices/structure        depth/fanout regressions
optimization        timing/power tradeoffs        one-metric overfitting
physical-aware      topo/congestion estimates     handoff delta surprises
closure             ECO order/regression          fixes break other corners

Synthesis deep dive

Physical-aware synthesis reduces logic-to-route surprise when correlation is monitored.

Concept diagram

PHYSICAL-AWARE LOOP

topo compile -> congestion hints -> handoff -> PD correlation

Metric graph

CORRELATION DELTA

logic view WNS      ███████
topo view WNS       █████
route trial WNS     ████

Reports and artifacts

• topo QoR

• congestion heatmap

• handoff manifest

• delta compare vs PD

Mini case study

Topo compile looked clean, but hotspot congestion predicted route failure and prevented late ECO churn.

Debug branches

• Check hotspot ownership

• Bound correlation drift

• Escalate if handoff assumptions stale

Senior review question

Ask: what evidence proves this QoR move is real and stable?

Key takeaways

• State exact run context (RTL, SDC, libs, switches) with every QoR claim.

• Re-run timing, area, and power regressions after each synthesis ECO.

Common pitfalls

• Comparing runs with mismatched constraints or library views.

• Timing-only fixes that violate power or area budgets.

• Skipping equivalence checks after structural changes.

Theory reinforcement

Physical-aware synthesis improves predictability between logic and implementation views.