Physical-Aware Debug: Worked Example

Worked example

Worked Example for Physical-Aware Debug focuses on logic-vs-physical delta isolation time, root-cause class distribution. The goal is to connect observed QoR movement to mechanism, ownership, and regression risk.

A weekly compile reports logic-vs-physical delta isolation time, root-cause class distribution regression. Instead of random knob tuning, start by proving whether input context changed and which mechanism dominates.

Sequence under inspection

SYNTHESIS FLOW — Physical-Aware Debug

RTL + constraints
      |
      v
elaboration + checks
      |
      v
mapping + optimization
      |
      v
QoR reports (timing/area/power)
      |
      v
incremental ECO + regression

Primary metric: logic-vs-physical delta isolation time, root-cause class distribution

Logic vs physical delta

compile QoR good, route QoR bad?
  -> model mismatch
  -> congestion issue
  -> true logic bottleneck

1. Capture baseline and regressed artifact pair.

2. Confirm manifest parity (RTL, SDC, libs, switches).

3. Pin first metric drift and mechanism hypothesis.

4. Reproduce with delta-debug checklist, topo/route compare, ownership board.

5. Apply one reversible fix and run matrix regression.

Did the fix hold?

BEFORE / AFTER QOR — Physical-Aware Debug

QoR score
  0 |                     --- target zone
 -1 |        ● regression
 -2 |             ● baseline
 -0.5|                  ● after fix
    +----------------------------------> iteration

Validate timing + area + power, not one number.

Synthesis deep dive

Physical-aware synthesis reduces logic-to-route surprise when correlation is monitored.

Concept diagram

PHYSICAL-AWARE LOOP

topo compile -> congestion hints -> handoff -> PD correlation

Metric graph

CORRELATION DELTA

logic view WNS      ███████
topo view WNS       █████
route trial WNS     ████

Reports and artifacts

• topo QoR

• congestion heatmap

• handoff manifest

• delta compare vs PD

Mini case study

Topo compile looked clean, but hotspot congestion predicted route failure and prevented late ECO churn.

Debug branches

• Check hotspot ownership

• Bound correlation drift

• Escalate if handoff assumptions stale

Senior review question

Ask: what evidence proves this QoR move is real and stable?

Key takeaways

• State exact run context (RTL, SDC, libs, switches) with every QoR claim.

• Re-run timing, area, and power regressions after each synthesis ECO.

Common pitfalls

• Comparing runs with mismatched constraints or library views.

• Timing-only fixes that violate power or area budgets.

• Skipping equivalence checks after structural changes.

Principal synthesis review addendum

Physical-aware debug classifies QoR regressions into modeling error, placement pressure, or true logic issues before ECO churn starts.

Metric: logic-vs-physical delta isolation time, root-cause class distribution