Synthesis & Logic Optimization · All levels

Topographical Synthesis: Debug Playbook

Debug Playbook for Topographical Synthesis.

Debug playbook

Debug Playbook for Topographical Synthesis focuses on topo-vs-logic WNS delta, estimated wirelength, congestion hotspots. The goal is to connect observed QoR movement to mechanism, ownership, and regression risk.

Synthesis debug finds the first causal drift, not the loudest downstream symptom.

Root-cause tree

diagram
ROOT-CAUSE TREE — Topographical Synthesis

topo-vs-logic WNS delta, estimated wirelength, congestion hotspots regressed
        |
   same RTL/constraints tag?
     /              \
   no                yes
   |                  |
input drift      transform side-effect
 /    \             /         \
SDC    libs      mapping      physical estimate
diff   diff      choice       mismatch
  1. Freeze baseline and regressed run manifests.

  2. Verify RTL/SDC/library deltas before transform tuning.

  3. Classify issue: constraints, mapping choice, physical estimate, or ECO side effect.

  4. Pick one minimal reversible change.

  5. Re-run full timing/area/power checks with ownership signoff.

Review memo template

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STAFF SYNTHESIS REVIEW MEMO — Physical-Aware Synthesis / Topographical Synthesis

1. Symptom
   - Watched metric: topo-vs-logic WNS delta, estimated wirelength, congestion hotspots
   - Affected compile run: <tag/build ID>
   - Impacted path/class: <critical group / power lane / area lane>
   - Database tags: <RTL, SDC, libs, switches>

2. Mechanism hypothesis
   - Primary mechanism: Topographical mode estimates physical effects during synthesis to reduce handoff surprises between logic and implementation views.
   - Competing hypothesis: <constraint drift, mapping choice, physical estimate mismatch>
   - Missing evidence: <report diff, dashboard trend, ownership board>

3. Proposed action
   - Minimal reversible change: <constraint patch, compile knob, ECO cell move>
   - Expected movement: <timing / area / power delta>
   - Regression risk: hold, power spike, leakage drift, formal mismatch

4. Signoff
   - Re-run artifact: topo compile report, estimated placement map, QoR delta log
   - Required owners: synthesis owner, PD owner, STA owner
   - Final decision: merge, rollback, or escalate

Synthesis deep dive

Physical-aware synthesis reduces logic-to-route surprise when correlation is monitored.

Concept diagram

diagram
PHYSICAL-AWARE LOOP

topo compile -> congestion hints -> handoff -> PD correlation

Metric graph

diagram
CORRELATION DELTA

logic view WNS      ███████
topo view WNS       █████
route trial WNS     ████

Reports and artifacts

  • topo QoR

  • congestion heatmap

  • handoff manifest

  • delta compare vs PD

Mini case study

Topo compile looked clean, but hotspot congestion predicted route failure and prevented late ECO churn.

Debug branches

  • Check hotspot ownership

  • Bound correlation drift

  • Escalate if handoff assumptions stale

Senior review question

Ask: what evidence proves this QoR move is real and stable?

Key takeaways

  • State exact run context (RTL, SDC, libs, switches) with every QoR claim.

  • Re-run timing, area, and power regressions after each synthesis ECO.

Common pitfalls

  • Comparing runs with mismatched constraints or library views.

  • Timing-only fixes that violate power or area budgets.

  • Skipping equivalence checks after structural changes.

Principal synthesis review addendum

Topographical mode estimates physical effects during synthesis to reduce handoff surprises between logic and implementation views.

Metric: topo-vs-logic WNS delta, estimated wirelength, congestion hotspots