Topographical Synthesis: Inputs & Outputs

Inputs and outputs contract

Inputs & Outputs for Topographical Synthesis focuses on topo-vs-logic WNS delta, estimated wirelength, congestion hotspots. The goal is to connect observed QoR movement to mechanism, ownership, and regression risk.

Synthesis closure fails when teams optimize against different assumptions. Treat these artifacts as a signed handoff contract.

INPUTS
  - RTL tag and compile switches
  - SDC / policy constraints
  - Library and operating views
  - Optional physical estimates (topo/congestion)

OUTPUTS
  - QoR timing/area/power reports
  - transform/mapping summaries
  - owner-tagged closure memo
  - regression matrix verdict

Flow sequence

SYNTHESIS FLOW — Topographical Synthesis

RTL + constraints
      |
      v
elaboration + checks
      |
      v
mapping + optimization
      |
      v
QoR reports (timing/area/power)
      |
      v
incremental ECO + regression

Primary metric: topo-vs-logic WNS delta, estimated wirelength, congestion hotspots

Ownership map

OWNERSHIP MAP — Topographical Synthesis

artifact              owner
----------------      -----------------
compile owner       synthesis owner
timing/power owner  PD owner
cross-team review   STA owner

Every QoR movement needs a named owner before ECO.

Synthesis deep dive

Physical-aware synthesis reduces logic-to-route surprise when correlation is monitored.

Concept diagram

PHYSICAL-AWARE LOOP

topo compile -> congestion hints -> handoff -> PD correlation

Metric graph

CORRELATION DELTA

logic view WNS      ███████
topo view WNS       █████
route trial WNS     ████

Reports and artifacts

• topo QoR

• congestion heatmap

• handoff manifest

• delta compare vs PD

Mini case study

Topo compile looked clean, but hotspot congestion predicted route failure and prevented late ECO churn.

Debug branches

• Check hotspot ownership

• Bound correlation drift

• Escalate if handoff assumptions stale

Senior review question

Ask: what evidence proves this QoR move is real and stable?

Key takeaways

• State exact run context (RTL, SDC, libs, switches) with every QoR claim.

• Re-run timing, area, and power regressions after each synthesis ECO.

Common pitfalls

• Comparing runs with mismatched constraints or library views.

• Timing-only fixes that violate power or area budgets.

• Skipping equivalence checks after structural changes.

Principal synthesis review addendum

Topographical mode estimates physical effects during synthesis to reduce handoff surprises between logic and implementation views.

Metric: topo-vs-logic WNS delta, estimated wirelength, congestion hotspots