Bind File Organization

One bind file per subsystem

Bind statements scattered through testbench files become unfindable. The convention that scales: a single <subsystem>_binds.sv file per subsystem, owned by DV, containing every bind that targets that subsystem's RTL — the one place to look when asking 'what is attached to this design?'

// dma_binds.sv — ALL verification attached to the DMA subsystem
`ifndef SYNTHESIS
`ifdef DMA_SVA_ON

// protocol checkers on external interfaces
bind dma_top  vr_checker #(.WIDTH(DATA_W)) chk_m_axis (
  .clk(clk), .rst_n(rst_n),
  .valid(m_axis_tvalid), .ready(m_axis_tready), .data(m_axis_tdata));

// whitebox checkers on internal blocks (every instance)
bind dma_fifo fifo_checker #(.DEPTH(DEPTH)) chk_fifo (.*);
bind dma_arb  arb_checker  #(.N(REQ_N))     chk_arb  (.*);

// instance-specific: only the descriptor engine
bind dma_top.u_desc_eng desc_checker chk_desc (
  .clk(clk), .rst_n(rst_n), .state_q(state_q));

`endif  // DMA_SVA_ON
`endif  // SYNTHESIS

Conventions in that file

• One file = one subsystem's binds — never mix subsystems; the file name says what it covers.

• Instance names prefixed chk_ — bound instances are instantly recognizable in hierarchy browsers and wave paths.

• Group by checker kind: external protocol checks first, whitebox module binds next, instance-specific binds last.

• Every bind file guarded by the same pair of macros — see below.

Compile order and build integration

A bind statement needs the target module and the checker module to be compiled (or at least declared) before binds elaborate. The robust ordering in a file list: RTL first, checker modules next, bind files last.

COMPILE ORDER [BUILD]

  dma.f (file list)
  ──────────────────────────────
  1.  rtl/dma_top.sv          ┐
      rtl/dma_fifo.sv         │  RTL — defines bind TARGETS
      rtl/dma_arb.sv          ┘
  2.  dv/checkers/vr_checker.sv    ┐
      dv/checkers/fifo_checker.sv  │  checker MODULES
      dv/checkers/arb_checker.sv   ┘
  3.  dv/binds/dma_binds.sv        ← BINDS last

  +define+DMA_SVA_ON               ← enable knob on the
                                     simulation command line
  Synthesis file list: items 1 only — binds never listed.

ifdef guarding

Two guards serve two purposes. `ifndef SYNTHESIS is defensive: even if a bind file leaks into a synthesis file list, the tool sees nothing (most synthesis flows define SYNTHESIS). `ifdef DMA_SVA_ON is the operational knob: regressions can disable a subsystem's checkers (during bring-up, or to isolate a performance problem) with one minus-define, no file-list surgery.

Ownership: DV holds the binds, RTL stays clean

• Bind files and checker modules live in the DV directory tree and go through DV code review — RTL reviews never see assertion churn.

• RTL engineers may read the bind file to learn what is watched, but changes route through DV — the bind file is the contract surface.

• When RTL renames a signal, the bind breaks loudly at elaboration — fix it in the bind file, never by asking RTL to keep legacy names.

• Tape-out checklists reference bind files directly: 'all dma_binds.sv checkers enabled and passing' is an auditable line item.

REPO LAYOUT [DV] [RTL]

  rtl/                         ← RTL ownership, synthesis-clean
    dma_top.sv  dma_fifo.sv  dma_arb.sv
  dv/
    checkers/                  ← reusable, bind-safe modules
      vr_checker.sv  fifo_checker.sv  arb_checker.sv
    binds/                     ← one file per subsystem
      dma_binds.sv  eth_binds.sv  pcie_binds.sv
    flists/
      dma_sim.f                ← RTL + checkers + binds
      dma_syn.f                ← RTL only

Key takeaways

• Centralize binds in one <subsystem>_binds.sv — the single answer to 'what is attached to this RTL?'

• Compile order: RTL targets, then checker modules, then bind files; binds never appear in synthesis lists.

• Double-guard every bind file: ifndef SYNTHESIS for safety, ifdef <SUBSYS>_SVA_ON as the runtime knob.

• Binds are DV-owned and DV-reviewed; RTL renames break binds loudly and get fixed on the DV side.

Common pitfalls

• Bind statements scattered across tb files — nobody can enumerate what is checked on a given block.

• Bind file compiled before the checker module — elaboration error that looks like a missing-module mystery.

• No SVA_ON knob — disabling checkers during bring-up means editing file lists, which never gets reverted.

• Letting a bind file into the synthesis list unguarded — at best an error, at worst tool-dependent surprises.