Review Checklist for Data Validity Debug focuses on invalid sample bursts, clipping incidents, stale-data escapes. The goal is to connect observed symptom to boundary mechanism, ownership, and signoff risk.
Boundary assumptions are versioned and signed.
Mode matrix (power/clock/reset/stress) is explicit.
Physical context (floorplan/package/power) is included where relevant.
Metric and artifact references are reproducible.
Waivers have owner, expiry, and mitigation.
Owners signed: signal-processing owner, RTL owner, system validation lead.
OWNERSHIP MAP — Data Validity Debug
artifact owner
---------------------- -----------------------------
integration artifact signal-processing owner
implementation artifact RTL owner
signoff artifact system validation lead
Every boundary issue needs a named owner before fixes start.Wrapper and sampling contracts determine data trustworthiness.
CONVERTER DATA FLOW
sampling clock -> wrapper -> sync boundary -> system consumerINVALID SAMPLE BURSTS
time ---> _|¯¯|__|¯¯¯|____|¯|_sample validity ratio
calibration convergence
CDC audit
overflow/stale sample counters
Mode transition changed sample phase and invalidated wrapper framing assumptions.
Sample timing contract
Calibration hook behavior
Wrapper CDC integrity
Ask: what boundary condition proves this topic is actually closed?
State boundary, mode, and evidence tag with every claim.
Always align analog, digital, and physical owners before signoff decisions.
Fixing averages while tails still fail.
Skipping package/supply evidence in jitter or SerDes issues.
Shipping with waivers that lack owner and expiration criteria.
Data validity must combine framing correctness, saturation/overflow signaling, and synchronization sanity so software trusts converter samples.
Metric: invalid sample bursts, clipping incidents, stale-data escapes
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