What this topic teaches

Sample Timing Contract converts analog-digital assumptions into a measurable engineering contract. Sampling quality depends on clock phase relationships, aperture uncertainty, and synchronization boundaries between converter clocks and system clocks. The hard part is proving which boundary broke first, under which mode, and with which evidence.

The senior-engineer question

When aperture budget compliance, sample alignment error, control-loop jitter moves, can you isolate the first failing boundary, identify owner, and define the smallest reversible change that proves root cause?

AMS CLOSURE FLOW — Sample Timing Contract

spec + handoff assumptions
        |
        v
boundary implementation (wrapper/cells/reset)
        |
        v
physical context (floorplan/power/package)
        |
        v
metrics + artifacts (jitter/BER/noise/validity)
        |
        v
root-cause classification -> bounded fix -> regression

Debug rule: always name mode, boundary, evidence tag, and owner.

Picture the boundary behavior

Start every study session by drawing the contract before opening logs or reports. The diagrams below are what to reproduce on whiteboard.

Sampling contract

sample edge alignment + aperture budget + CDC boundary
=> valid digital sample interpretation

Boundary sequence

AMS BOUNDARY SEQUENCE — Sample Timing Contract

analog macro -> wrapper / boundary cell -> synchronizer or sampler -> digital consumer
      |                 |                         |                     |
  analog assumptions    legal voltage/state       clock/reset contract   protocol/data validity

metric under watch: aperture budget compliance, sample alignment error, control-loop jitter

Who owns which layer

AMS OWNERSHIP LAYERS — Sample Timing Contract

layer                owns                                failure mode
------------------   ----------------------------------  --------------------------
spec contract         clocks/resets/interfaces            hidden assumption drift
wrapper logic         synchronizers/framing/flags         silent data corruption
physical integration  floorplan/isolation/power           coupled noise and droop
signoff governance    waivers/checklists/dashboard        release with blind spots
closure               debug order + regression            fix regresses another mode

Evidence to collect

• Primary metric: aperture budget compliance, sample alignment error, control-loop jitter.

• Primary artifact: timing contract table, phase alignment report, calibration captures.

• Owners to bring into review: system architect, timing owner, ADC/DAC owner.

• One tagged reproduction and one reduced reproducer.

• Cross-check from at least two evidence planes: functional and physical/signoff.

Ownership map

OWNERSHIP MAP — Sample Timing Contract

artifact                  owner
----------------------    -----------------------------
integration artifact    system architect
implementation artifact timing owner
signoff artifact        ADC/DAC owner

Every boundary issue needs a named owner before fixes start.

Subpages in this topic

Each topic includes mechanism, contract I/O, reports, debug, worked example, pitfalls, interview, checklist, theory, design-space, extended case study, walkthrough, comparison matrix, software view, and silicon PPA impact.

Key takeaways

• Carry boundary and mode context with every metric.

• Prove mechanism with tagged evidence before changing silicon-facing logic.

• Close with explicit owner-aligned regression criteria.

Common pitfalls

• Assuming lock/ready/valid means healthy behavior.

• Ignoring package and power contributors in jitter/SerDes issues.

• Waivers without expiry, owner, or mitigation plan.

AMS deep dive

Wrapper and sampling contracts determine data trustworthiness.

Concept diagram

CONVERTER DATA FLOW

sampling clock -> wrapper -> sync boundary -> system consumer

Metric graph

INVALID SAMPLE BURSTS

time --->  _|¯¯|__|¯¯¯|____|¯|_

Reports and artifacts

• sample validity ratio

• calibration convergence

• CDC audit

• overflow/stale sample counters

Mini case study

Mode transition changed sample phase and invalidated wrapper framing assumptions.

Debug branches

• Sample timing contract

• Calibration hook behavior

• Wrapper CDC integrity

Senior review question

Ask: what boundary condition proves this topic is actually closed?

Key takeaways

• State boundary, mode, and evidence tag with every claim.

• Always align analog, digital, and physical owners before signoff decisions.

Common pitfalls

• Fixing averages while tails still fail.

• Skipping package/supply evidence in jitter or SerDes issues.

• Shipping with waivers that lack owner and expiration criteria.