Sample Timing Contract: Software / Programmer View

RTL / firmware view

Framing and CDC strategy decides whether samples remain trustworthy.

What engineers observe

• Intermittent bring-up failures

• Mode-transition instability

• Data-validity bursts

Design structure impact

• Reset choreography

• Clock/control handshakes

• Wrapper framing semantics

Toolchain interaction

• Synthesis/CDC assumptions must match analog contract

• Beware hidden mode-only paths

Mitigations

• Explicit wrappers

• Observable state machines

• Cross-team interface reviews

RTL / FW — Sample Timing Contract
// mode switch sequencing changed -> re-check boundary assumptions and regressions

Layer the code touches

AMS OWNERSHIP LAYERS — Sample Timing Contract

layer                owns                                failure mode
------------------   ----------------------------------  --------------------------
spec contract         clocks/resets/interfaces            hidden assumption drift
wrapper logic         synchronizers/framing/flags         silent data corruption
physical integration  floorplan/isolation/power           coupled noise and droop
signoff governance    waivers/checklists/dashboard        release with blind spots
closure               debug order + regression            fix regresses another mode

AMS deep dive

Wrapper and sampling contracts determine data trustworthiness.

Concept diagram

CONVERTER DATA FLOW

sampling clock -> wrapper -> sync boundary -> system consumer

Metric graph

INVALID SAMPLE BURSTS

time --->  _|¯¯|__|¯¯¯|____|¯|_

Reports and artifacts

• sample validity ratio

• calibration convergence

• CDC audit

• overflow/stale sample counters

Mini case study

Mode transition changed sample phase and invalidated wrapper framing assumptions.

Debug branches

• Sample timing contract

• Calibration hook behavior

• Wrapper CDC integrity

Senior review question

Ask: what boundary condition proves this topic is actually closed?

Key takeaways

• State boundary, mode, and evidence tag with every claim.

• Always align analog, digital, and physical owners before signoff decisions.

Common pitfalls

• Fixing averages while tails still fail.

• Skipping package/supply evidence in jitter or SerDes issues.

• Shipping with waivers that lack owner and expiration criteria.

Principal AMS review addendum

Sampling quality depends on clock phase relationships, aperture uncertainty, and synchronization boundaries between converter clocks and system clocks.

Metric: aperture budget compliance, sample alignment error, control-loop jitter