Review checklist

Review Checklist for Sample Timing Contract focuses on aperture budget compliance, sample alignment error, control-loop jitter. The goal is to connect observed symptom to boundary mechanism, ownership, and signoff risk.

• Boundary assumptions are versioned and signed.

• Mode matrix (power/clock/reset/stress) is explicit.

• Physical context (floorplan/package/power) is included where relevant.

• Metric and artifact references are reproducible.

• Waivers have owner, expiry, and mitigation.

• Owners signed: system architect, timing owner, ADC/DAC owner.

Sign-off ownership

OWNERSHIP MAP — Sample Timing Contract

artifact                  owner
----------------------    -----------------------------
integration artifact    system architect
implementation artifact timing owner
signoff artifact        ADC/DAC owner

Every boundary issue needs a named owner before fixes start.

AMS deep dive

Wrapper and sampling contracts determine data trustworthiness.

Concept diagram

CONVERTER DATA FLOW

sampling clock -> wrapper -> sync boundary -> system consumer

Metric graph

INVALID SAMPLE BURSTS

time --->  _|¯¯|__|¯¯¯|____|¯|_

Reports and artifacts

• sample validity ratio

• calibration convergence

• CDC audit

• overflow/stale sample counters

Mini case study

Mode transition changed sample phase and invalidated wrapper framing assumptions.

Debug branches

• Sample timing contract

• Calibration hook behavior

• Wrapper CDC integrity

Senior review question

Ask: what boundary condition proves this topic is actually closed?

Key takeaways

• State boundary, mode, and evidence tag with every claim.

• Always align analog, digital, and physical owners before signoff decisions.

Common pitfalls

• Fixing averages while tails still fail.

• Skipping package/supply evidence in jitter or SerDes issues.

• Shipping with waivers that lack owner and expiration criteria.

Principal AMS review addendum

Sampling quality depends on clock phase relationships, aperture uncertainty, and synchronization boundaries between converter clocks and system clocks.

Metric: aperture budget compliance, sample alignment error, control-loop jitter