Sample Timing Contract: Theory Deep Dive

Foundational theory

Sample Timing Contract is central to ADC / DAC Interfaces. Sampling quality depends on clock phase relationships, aperture uncertainty, and synchronization boundaries between converter clocks and system clocks. Senior AMS owners always tie observed failure to boundary assumptions, ownership, and measurable evidence before changing RTL or layout.

Core concepts explained

• Sampling quality depends on clock phase relationships, aperture uncertainty, and synchronization boundaries between converter clocks and system clocks.

• Primary metric: aperture budget compliance, sample alignment error, control-loop jitter

• Primary artifact: timing contract table, phase alignment report, calibration captures

• Owners: system architect, timing owner, ADC/DAC owner

• Boundary and mode context are mandatory for any claim.

• Treat lock/ready/valid bits as evidence, not proof of health.

Why this matters at signoff

At tapeout and bring-up, Sample Timing Contract escapes are expensive to fix. Converter trust depends on sampling contracts and wrapper discipline. Wrong diagnosis burns schedule across analog, digital, and package teams.

Mental model

sample edge alignment + aperture budget + CDC boundary
=> valid digital sample interpretation

Worked intuition

1. Name boundary and product mode where failure appears.

2. Open aperture budget compliance, sample alignment error, control-loop jitter and identify worst scenario.

3. Trace clocks/resets/config from analog macro to digital consumer.

4. Verify wrapper and handoff assumptions on the failing path.

5. Collect timing contract table, phase alignment report, calibration captures and freeze evidence tags.

6. Classify root cause: contract gap, physical coupling, sequencing bug, or tool-view mismatch.

7. Propose minimal bounded change plus cross-domain regression.

Common misconceptions

• Lock high means clock quality is automatically good.

• Boundary cells are one-time checklist items, not runtime risks.

• SerDes training failure is always firmware.

• If average metric is healthy, there is no silicon risk.

Visual reinforcement

Sampling contract

sample edge alignment + aperture budget + CDC boundary
=> valid digital sample interpretation

Layer responsibilities

AMS OWNERSHIP LAYERS — Sample Timing Contract

layer                owns                                failure mode
------------------   ----------------------------------  --------------------------
spec contract         clocks/resets/interfaces            hidden assumption drift
wrapper logic         synchronizers/framing/flags         silent data corruption
physical integration  floorplan/isolation/power           coupled noise and droop
signoff governance    waivers/checklists/dashboard        release with blind spots
closure               debug order + regression            fix regresses another mode

AMS deep dive

Wrapper and sampling contracts determine data trustworthiness.

Concept diagram

CONVERTER DATA FLOW

sampling clock -> wrapper -> sync boundary -> system consumer

Metric graph

INVALID SAMPLE BURSTS

time --->  _|¯¯|__|¯¯¯|____|¯|_

Reports and artifacts

• sample validity ratio

• calibration convergence

• CDC audit

• overflow/stale sample counters

Mini case study

Mode transition changed sample phase and invalidated wrapper framing assumptions.

Debug branches

• Sample timing contract

• Calibration hook behavior

• Wrapper CDC integrity

Senior review question

Ask: what boundary condition proves this topic is actually closed?

Key takeaways

• State boundary, mode, and evidence tag with every claim.

• Always align analog, digital, and physical owners before signoff decisions.

Common pitfalls

• Fixing averages while tails still fail.

• Skipping package/supply evidence in jitter or SerDes issues.

• Shipping with waivers that lack owner and expiration criteria.

Theory reinforcement

Converter trust depends on sampling contracts and wrapper discipline.