Sample Timing Contract: Expanded Case Study

Extended case study

Signoff review: aperture budget compliance, sample alignment error, control-loop jitter regressed after a change touching Sample Timing Contract.

Background

Team had prior closure; latest integration run shows instability concentrated in one operating condition.

Symptoms observed

• aperture budget compliance, sample alignment error, control-loop jitter degradation

• Cross-team disagreement on root cause

• Directed tests pass but system scenario fails

Investigation timeline

1. Hour 0: freeze data tags, firmware build, and environmental conditions

2. Hour 1: diff boundary assumptions and handoff revisions

3. Hour 2: isolate first failing mode and trigger sequence

4. Hour 3: correlate waveform/log/report evidence

5. Hour 4: classify root cause and ownership

6. Hour 5: apply bounded fix

7. Hour 6: execute full regression and issue signoff memo

Root cause

Root cause tied to Sample Timing Contract: Sampling quality depends on clock phase relationships, aperture uncertainty, and synchronization boundaries between converter clocks and system clocks.

Fix and validation

• Bounded RTL/config/layout correction

• Re-run timing contract table, phase alignment report, calibration captures

• Full cross-domain regression matrix

Lessons learned

• Tag everything

• Mechanism before commands

• No signoff without owner agreement

CASE STUDY — Sample Timing Contract
baseline metric / regressed metric / post-fix metric

Sequence under stress

AMS BOUNDARY SEQUENCE — Sample Timing Contract

analog macro -> wrapper / boundary cell -> synchronizer or sampler -> digital consumer
      |                 |                         |                     |
  analog assumptions    legal voltage/state       clock/reset contract   protocol/data validity

metric under watch: aperture budget compliance, sample alignment error, control-loop jitter

AMS deep dive

Wrapper and sampling contracts determine data trustworthiness.

Concept diagram

CONVERTER DATA FLOW

sampling clock -> wrapper -> sync boundary -> system consumer

Metric graph

INVALID SAMPLE BURSTS

time --->  _|¯¯|__|¯¯¯|____|¯|_

Reports and artifacts

• sample validity ratio

• calibration convergence

• CDC audit

• overflow/stale sample counters

Mini case study

Mode transition changed sample phase and invalidated wrapper framing assumptions.

Debug branches

• Sample timing contract

• Calibration hook behavior

• Wrapper CDC integrity

Senior review question

Ask: what boundary condition proves this topic is actually closed?

Key takeaways

• State boundary, mode, and evidence tag with every claim.

• Always align analog, digital, and physical owners before signoff decisions.

Common pitfalls

• Fixing averages while tails still fail.

• Skipping package/supply evidence in jitter or SerDes issues.

• Shipping with waivers that lack owner and expiration criteria.

Principal AMS review addendum

Sampling quality depends on clock phase relationships, aperture uncertainty, and synchronization boundaries between converter clocks and system clocks.

Metric: aperture budget compliance, sample alignment error, control-loop jitter