Skip to content
DenseChip
Learn
PracticeCode labInterview

DenseChip

Navigate

Menu

LearnPracticeCode labInterview

Tools

All toolsSV editorCode repoResume
DenseChip

Practice, courses, and chip-design tools in one focused workspace.

LearnPracticeCode labInterviewToolsLearning paths

© 2026 DenseChip

AboutContactPrivacyTerms
Skip to lesson

Course contents

  • How to Use This Course
  • Reading Path
  • Cache Coherency Glossary
  • The Shared Course Model
  • Cache Coherency Revision Sheet
  • Why Coherence Exists8
  • States and Protocols12
  • Transactions12
  • Races and Controller Design8
  • Progress and the Fabric16
  • Ordering and Synchronization12
  • Performance and Scalability12
  • Real Protocols12
    • MESI Versus MOESI Trade-Offs
    • CHI and ACE Message Models
      • ACE on the Course Model
      • CHI Nodes and Channels
      • CHI Transaction Walkthroughs
      • Mapping ACE and CHI States
    • TileLink and Custom Coherence Extensions
  • SoC Integration12
  • Power, Clocking and Reliability12
  • Verification12
  • Debug and Bring-up12
  • Interview and Design Review17
  • Capstone: A Coherent Model Lab5
Loading lesson

‹CHI and ACE Message Models
  1. Topics
  2. Cache Coherency
  3. Real Protocols
  4. CHI and ACE Message Models
  5. ACE on the Course Model

Part 8 · Real Protocols · All levels

ACE on the Course Model

ACE (IHI 0022 Issue H.c): snoop channels AC, CR and CD, five cache states, coherent transactions, CRRESP bits, RACK and WACK, and a ReadShared that hits a UniqueDirty line.

On this page

    What does ACE add to AXI to make caches coherent?

    ACE keeps the five AXI channels (AR, R, AW, W, B) and adds three snoop channels from the interconnect to each caching manager: the snoop address channel AC (the snoop request), the snoop response channel CR (CRRESP) and the snoop data channel CD (a full line when DataTransfer is set). All rules below are from the AMBA AXI and ACE Protocol Specification, Arm IHI 0022, Issue H.c.

    ACE has no separate home node. The interconnect plays H: it orders transactions to the same line, issues the snoops, collects responses and data, builds the response to the initiating manager and performs any memory access (section D6.1). Whether it keeps a record of holders is optional: Chapter D10 describes an external snoop filter. In this lesson's tables we assume one, so the H column reads like the course directory; a pure snooping interconnect keeps no such record (Hybrids and Snoop Filters).

    Five states, and the course names

    ACE state

    Rule in IHI 0022H.c, Table D1-1

    Course state

    UniqueDirty (UD)

    Only this cache, modified relative to memory, may store without telling others

    M

    SharedDirty (SD)

    Possibly shared, modified, this cache must update memory eventually

    O (MOESI)

    UniqueClean (UC)

    Only this cache, not modified, may store without telling others

    E (MESI, MOESI)

    SharedClean (SC)

    Possibly shared, not responsible for memory; whether the line is modified is not known

    S

    Invalid (I)

    Not present

    I

    Two rules in Table D1-1's surrounding text matter for traces: a line updated relative to memory is Dirty in exactly one cache, and a cache that discards a copy need not tell anyone, so a Shared line may in fact be held by only one cache. That is silent clean eviction, the variant in Clean Eviction: Silent or Notified.

    Transactions mapped to course messages

    ACE transaction

    Channels

    Course equivalent

    Rule worth remembering

    ReadShared

    AR, R

    GetS

    May end UC, UD, SC or SD: all four RRESP[3:2] values are permitted (Table D6-2)

    ReadClean

    AR, R

    GetS that refuses dirty data

    PassDirty must be LOW, so the interconnect writes back any dirty data it receives

    ReadNotSharedDirty

    AR, R

    GetS from a cache without SD

    RRESP must not be IsShared plus PassDirty

    ReadUnique

    AR, R

    GetM from I

    IsShared must be LOW, other copies invalidated

    CleanUnique

    AR, R

    GetM from S (upgrade, no data)

    Removes other copies, dirty copies are written to memory, used for a partial-line store

    MakeUnique

    AR, R

    GetM without data

    Only for a full-line store, recommended snoop is MakeInvalid

    WriteBack

    AW, W, B

    PutM

    Dirty line written back, the cache keeps no copy

    WriteClean

    AW, W, B

    No single message

    Dirty line written to memory while the cache keeps a clean copy

    Evict

    AW, B

    PutS or PutE

    Useful only when the interconnect has a snoop filter; a manager may still evict a clean line silently

    The snoop the interconnect sends is recommended by Tables D5-1 and D6-1: ReadShared recommends a ReadShared snoop, ReadUnique a ReadUnique snoop, CleanUnique a CleanInvalid snoop, MakeUnique a MakeInvalid snoop. WriteBack, WriteClean and Evict cause no snoop.

    The snoop response bits

    CRRESP bit

    Meaning (Table D3-21)

    [0] DataTransfer

    A full line follows on CD

    [1] Error

    The snooped line is in error

    [2] PassDirty

    The line was Dirty and responsibility for writing it back passes to the initiator or the interconnect

    [3] IsShared

    The snooped cache keeps a copy

    [4] WasUnique

    The line was Unique before the snoop. Optional: a cache may hold it LOW permanently

    PassDirty without DataTransfer is illegal. Snoop responses on CR return in the same order as the snoops on AC. Snoop data on CD is also in AC order. CR and CD are independent of each other, so the data may arrive before or after its CRRESP; the trace shows one legal order (D3.9).

    Worked case: ReadShared hits UniqueDirty

    Keep the roles of the MSI dirty read: X started at 0, C0 acquired M and stored 1, so C0 holds UD / 1 and memory = 0. C1 issues ReadShared. For this snoop on a dirty line, Table D3-22 lists IsShared, PassDirty and DataTransfer all set (pass dirty data and keep a copy) as the expected response, so C0 goes UD to SC. The interconnect then has two legal choices. This trace takes the one that matches the course: it writes memory itself and does not pass dirty to C1 (permitted by D6.5.2). At step 3, CRRESP IsShared = 1 tells H that C0 kept a copy, but H keeps exclusive(C0) until it has written memory, because S{C0} in the course notation claims memory is current. C1's read stays pending until RACK.

    C1 sends ReadShared, the interconnect snoops C0, C0 keeps a clean shared copy and passes dirty data, the interconnect writes memory, returns shared data to C1, and C1 acknowledges with RACK.
    ACE ReadShared on a UniqueDirty line, with the interconnect (H) writing memory. RACK tells H that C1's read is complete.

    Step

    C0 state / value

    C1 state / value

    H directory

    Memory

    Newest data

    Checkpoint

    UD / 1

    I / -

    exclusive(C0)

    0

    C0: 1

    1. ReadShared at H

    UD / 1

    IS^D / -

    exclusive(C0), pend ReadShared C1

    0

    C0: 1

    2. Snoop at C0

    SC / 1

    IS^D / -

    exclusive(C0), pend ReadShared C1

    0

    C0: 1, CD data(1) in flight to H

    3. CRRESP at H

    SC / 1

    IS^D / -

    exclusive(C0), pend ReadShared C1

    0

    C0: 1, CD data(1) in flight to H

    4. CD data at H

    SC / 1

    IS^D / -

    exclusive(C0), pend ReadShared C1

    0

    C0 and H buffer: 1

    H writes memory

    SC / 1

    IS^D / -

    S{C0}, pend ReadShared C1

    1

    C0 and memory: 1, R data(1) in flight to C1

    5. R data at C1

    SC / 1

    SC / 1

    S{C0}, pend ReadShared C1

    1

    C0, C1 and memory: 1

    6. RACK at H

    SC / 1

    SC / 1

    S{C0,C1}

    1

    C0, C1 and memory: 1

    ACE step

    Course MSI step

    Difference

    1. ReadShared

    1. GetS

    None in role

    2. ReadShared snoop

    2. Fwd-GetS

    ACE snoops are named after the request type

    3. CRRESP and 4. CD data

    3. Data to H

    ACE splits the response bits and the data onto two channels

    H writes memory

    H writes memory

    Same

    5. R data, IsShared=1

    4. Data(S permission)

    IsShared is the permission: the line must be held Shared

    6. RACK

    (assumed) grant delivered

    RACK is the real completion the course model assumed

    RACK is the course's grant-delivery rule made explicit. Section D6.2 requires that, once the interconnect has sent a response to a manager, it must not snoop that manager for the same line until it has received the matching RACK (or WACK for writes). The other choice for the interconnect, and the one the specification recommends when nothing forces a write, is RRESP IsShared=1, PassDirty=1: C1 ends SD / 1, C0 SC / 1, memory stays 0, and C1 has become the dirty-responsible holder, which is MOESI dirty sharing with the responsibility moved to the reader (MOESI and Dirty Sharing).

    Common pitfall

    Reading SC as 'memory is current'. ACE says only that an SC cache is not responsible for memory. In the PassDirty=1 ending, C0 is SC / 1 while memory = 0, and C1 (SD) owes the write.

    Interview

    Give the CRRESP for a ReadShared snoop on a UD line, then the two RRESP choices the interconnect has and who ends up owing the memory write in each.

    Check yourself C1's ReadShared returns RRESP IsShared=0, PassDirty=1. What state does C1 install, and what happened to C0?

    UD: no other copy is kept and dirty responsibility is passed to C1. So C0 must have invalidated its copy and passed dirty data (CRRESP IsShared=0, PassDirty=1, DataTransfer=1), which Table D3-22 permits for a ReadShared snoop. Memory is still stale, and C1 must write back eventually.

    Related topics

    • Shared course model

    • The course MSI dirty read

    • Next: CHI nodes and channels

    Previous

    90 / 167

    Next: CHI Nodes and Channels

    Up next

    Up nextCHI Nodes and Channels

    Sign in to save progress

    Practice this lessonReport an error

    See also

    • CHI Transaction Walkthroughs
    • Mapping ACE and CHI States