TileLink is an open interconnect standard with a cached conformance level (TL-C). Its vocabulary looks unfamiliar: five lettered channels, permissions called Branch, Trunk and Tip, and messages called Acquire, Probe and Release. Underneath, it answers the same questions as the course protocol: who serializes a line, who may supply data, and which message tells the home that a transaction is complete. This topic maps it onto the course model, then uses what you learned to judge extensions that teams add to any base protocol.
Facts about TileLink are taken from the SiFive TileLink Specification, version 1.8.1 (27 January 2020). Where this topic compares with ACE and CHI it uses Arm IHI 0022 Issue H.c and Arm IHI 0050 Issue E.a, which the CHI and ACE lessons cover in depth.
Lesson | After it you can... |
|---|---|
Name the conformance levels, the five channels and their priority order, and map None, Branch, Trunk and Tip onto course states. | |
Translate Acquire, Probe and Release flows into course messages, row by row, including the GrantAck completion. | |
Evaluate a proposed extension: state table diff, message class, new transient states and a model check. | |
Compare the course model, ACE, CHI and TileLink on serialization, channels, states, completion, data routing and retry. |
Suggested order: permissions, then transactions, then the comparison sheet. Read the extensions lesson last, because it uses the channel-priority argument from the first lesson.
With a Probe on channel B whose parameter caps the cache's permission at None (toN). The cache answers on channel C with ProbeAck (or ProbeAckData if it must return dirty data), reporting the transition it made, for example BtoN. That pair plays the role of Inv and Inv-Ack.