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Course contents

  • How to Use This Course
  • Reading Path
  • Cache Coherency Glossary
  • The Shared Course Model
  • Cache Coherency Revision Sheet
  • Why Coherence Exists8
  • States and Protocols12
  • Transactions12
  • Races and Controller Design8
  • Progress and the Fabric16
  • Ordering and Synchronization12
  • Performance and Scalability12
  • Real Protocols12
    • MESI Versus MOESI Trade-Offs
    • CHI and ACE Message Models
    • TileLink and Custom Coherence Extensions
      • TileLink Permissions
      • TileLink Transactions
      • Custom Extensions and Their Risks
      • Protocol Comparison Sheet
  • SoC Integration12
  • Power, Clocking and Reliability12
  • Verification12
  • Debug and Bring-up12
  • Interview and Design Review17
  • Capstone: A Coherent Model Lab5
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‹TileLink and Custom Coherence Extensions
  1. Topics
  2. Cache Coherency
  3. Real Protocols
  4. TileLink and Custom Coherence Extensions
  5. Protocol Comparison Sheet

Part 8 · Real Protocols · All levels

Protocol Comparison Sheet

The course model, AMBA ACE, AMBA CHI and TileLink side by side: serialization point, channels, states, completion, direct data transfer and retry.

On this page

    Which protocol answers each course question how?

    One sheet for revision and interviews. Columns: the course model, AMBA ACE (Arm IHI 0022 Issue H.c), AMBA 5 CHI (Arm IHI 0050 Issue E.a) and TileLink (SiFive TileLink Specification, version 1.8.1 (27 January 2020)). The TileLink column is taken from that specification's text. The ACE and CHI columns summarise what the CHI and ACE lessons teach, and the ACE and CHI cells were checked against those issues.

    Question

    Course model

    ACE (IHI 0022 H.c)

    CHI (IHI 0050 E.a)

    TileLink 1.8.1

    Serialization point

    H (directory and memory controller)

    The interconnect

    The Home Node (HN-F), the point of coherence and serialization

    The slave agent managing the address, at each level of the tree

    Channels or classes

    Request, forward, response classes, no FIFO assumed

    AXI AR, R, AW, W, B plus snoop AC, CR, CD

    REQ, RSP, SNP and DAT

    A, B, C, D, E with priority A < B < C < D < E

    Cache states

    MSI, MESI or MOESI, named per lesson

    UniqueDirty, SharedDirty, UniqueClean, SharedClean, Invalid

    I, UC, UCE, UD, UDP, SC, SD

    None, Branch, Trunk, Tip. Dirty is not part of the permission.

    Completion acknowledgement

    Assumed delivery in Parts 1-3, a Complete message in Part 4

    RACK after the last read data beat, WACK after the write response, sent for every transaction. The interconnect must not snoop that manager for the same line until it arrives (IHI 0022H.c D6.2, D6.2.1).

    CompAck from the requester for Read and Dataless transactions; the HN-F sends no further snoop to the line until it arrives (not for ReadOnce* or ReadNoSnp). For CopyBack writes the write data acts as an implicit CompAck (IHI 0050E.a 2.8.3, 4.11.2).

    GrantAck on E, mandatory for every Grant

    Direct data transfer

    Three-hop and four-hop variants

    No: snoop data (CD) goes to the interconnect, which returns it on R

    Yes: DCT (from the snooped cache), DMT (from the memory node)

    No: ProbeAckData goes to the slave, Grant always comes from it

    Retry or credits

    Optional: retries, NACKs and credits in Part 4

    No retry. VALID/READY handshakes on every channel. The interconnect may hold AR requests while snoops complete, but WriteBack, WriteClean, WriteEvict and Evict must progress without waiting for snoops (IHI 0022H.c D6.6.1).

    RetryAck with protocol credits (PCrdGrant), link-layer credits

    No retry. Ready/valid flow control with channel priority rules. Grant can be denied (d_denied).

    Who can revoke a writable copy

    H, by Inv or Fwd-GetM

    Interconnect, by snoop on AC

    HN-F, by snoop on SNP

    Slave, by Probe on B with toN or toB

    Read the table by column for a protocol and by row for a design question. Two rows carry most interview value. Completion: all three real protocols need an explicit acknowledgement from the requester for at least some transactions, because none of them assumes the ordered delivery that would make it unnecessary. Direct transfer: only CHI sends data straight from the snooped cache to the requester. TileLink and ACE always route it through the home, which costs a leg on the critical path and saves the home from tracking a transfer it did not perform.

    What the sheet does not show

    Equal names do not imply equal behaviour. ACE SharedDirty and CHI SD resemble the course's MOESI O, but which agent must write back, and when, follows each specification's rules. CHI UCE and UDP have no course equivalent at all. TileLink's Trunk exists only in a hierarchy. Use the sheet to find the right question, then read the lesson and the specification section for the answer.

    Exercise

    Course model, C0 holds X dirty (course M / 1, TileLink T), C1 holds nothing, memory = 0. C1 wants to write X. For each protocol, write the message sequence up to the moment H may start another transaction for X, and count the legs on C1's critical path (before C1 can use the line) separately from the legs after it.

    Protocol

    Sequence to write

    Hint

    Course, four-hop

    GetM, Fwd-GetM, Data to H, Data to C1

    Compare Three-Hop Versus Four-Hop

    TileLink 1.8.1

    AcquireBlock NtoT, ProbeBlock toN, ProbeAckData TtoN, GrantData toT, GrantAck

    Where is GrantAck relative to C1's first store?

    CHI with DCT

    ReadUnique, SnpUniqueFwd, CompData_UD_PD (C0 straight to C1), SnpResp_I_Fwded_UD_PD (C0 to H), CompAck

    SnpUniqueFwd: a dirty snoopee passes dirty to the requester, not the home (IHI 0050E.a Table 4-35). Which message lets the home finish?

    Check yourself For the TileLink case, how many legs are on C1's critical path, and why does GrantAck not add one?

    Four: AcquireBlock, ProbeBlock, ProbeAckData, GrantData. C1 can store as soon as GrantData arrives. GrantAck goes back to H afterwards, so it only delays H's next transaction for X, not C1. That is the same four-hop count as the course's H-buffered route, plus one completion leg off the critical path.

    Common pitfall

    Copying one protocol's acknowledgement rules into a design that uses another. A CHI requester's CompAck, an ACE RACK and a TileLink GrantAck all signal completion, but which transactions need them, and what the home may do before they arrive, differ by specification.

    Interview

    When asked to compare protocols, pick two rows that matter for the question (usually completion and data routing), state each protocol's rule with the specification name, and explain the trade-off on the course model.

    Related topics

    • Shared course model

    • TileLink flows on the course model

    • Mapping ACE and CHI states

    • CHI transaction walkthroughs

    • ACE on the course model

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    See also

    • TileLink Permissions
    • TileLink Transactions