Which course state is UD, and which course state is UCE?

ACE and CHI name states by three properties: Unique or Shared, Clean or Dirty, and (CHI only) whether the data bytes are all valid. The course names states by protocol letters. The table translates them. ACE states are from Table D1-1 of the AMBA AXI and ACE Protocol Specification, Arm IHI 0022, Issue H.c; CHI states from section 4.1 of the AMBA 5 CHI Architecture Specification, Arm IHI 0050, Issue E.a. Neither document prints a MOESI mapping; the course column is this course's correspondence, defined by the properties.

SC needs care. In course MSI and MESI, S means memory is current. In ACE and CHI, SC only means this cache is not responsible for memory: another cache may hold SD. That is the same as S beside O in MOESI (MOESI and Dirty Sharing).

The two CHI states with no course equivalent

UCE (Unique Clean Empty): unique permission, no valid bytes. A cache gets there on purpose, by asking for permission without data before overwriting a line, or by accident, when its shared copy is invalidated while it waits for an upgrade. On a snoop that asks for data, a UCE line must not return or forward data, so the home must take the data from memory, which is current because no cache is dirty.

UDP (Unique Dirty Partial): the cache has stored to part of a UCE line. On eviction the dirty bytes must be merged with the rest from the next level or memory. On a snoop it must return its data to the home and must not forward it directly to a requester, because the requester needs a full line and only the home can do the merge.

The course model has neither because its I-to-M transaction always delivers a full line. A course-model checker run on CHI traces needs a third coordinate (empty, partial, full) and the merge rule, or it will treat UDP data as the whole line.

Subsets

CHI permits a cache to implement a subset of the seven states (section 4.1), and provides ReadNotSharedDirty for caches without SD. ACE was designed to connect managers running MESI, MOESI and other subsets (section D1.1). A MESI cache simply never installs SD; the interconnect or home must not hand it one. CHI also defines DoNotGoToSD (section 4.10) so a snooped cache without SD is never left in SD.

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def chi_name(valid, unique, dirty, full=True):
    if not valid:
        return "I"
    if unique and not full:
        return "UDP" if dirty else "UCE"
    return ("U" if unique else "S") + ("D" if dirty else "C")

COURSE = {"I": (False, False, False), "S": (True, False, False),
          "E": (True, True, False), "M": (True, True, True),
          "O": (True, False, True)}
expect = {"I": "I", "S": "SC", "E": "UC", "M": "UD", "O": "SD"}
for s, props in COURSE.items():
    assert chi_name(*props) == expect[s]
assert chi_name(True, True, False, full=False) == "UCE"
assert chi_name(True, True, True, full=False) == "UDP"

def legal(states):
    uniq = [s for s in states if s.startswith("U")]
    dirty = [s for s in states if s in ("UD", "UDP", "SD")]
    valid = [s for s in states if s != "I"]
    if uniq and len(valid) > 1:
        return False          # a Unique line is in one cache only
    return len(dirty) <= 1    # dirty in at most one cache

assert legal(["SD", "SC"]) and legal(["UCE", "I"]) and legal(["SC", "SC"])
assert not legal(["UC", "SC"])
assert not legal(["SD", "SD"])
print("PASS: course states map by properties, UCE and UDP need a fullness bit")

Related topics

• Shared course model

• MOESI and the O state

• ACE states in a trace