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Course contents

  • How to Use This Course
  • Reading Path
  • Cache Coherency Glossary
  • The Shared Course Model
  • Cache Coherency Revision Sheet
  • Why Coherence Exists8
  • States and Protocols12
  • Transactions12
  • Races and Controller Design8
  • Progress and the Fabric16
  • Ordering and Synchronization12
  • Performance and Scalability12
  • Real Protocols12
    • MESI Versus MOESI Trade-Offs
    • CHI and ACE Message Models
    • TileLink and Custom Coherence Extensions
      • TileLink Permissions
      • TileLink Transactions
      • Custom Extensions and Their Risks
      • Protocol Comparison Sheet
  • SoC Integration12
  • Power, Clocking and Reliability12
  • Verification12
  • Debug and Bring-up12
  • Interview and Design Review17
  • Capstone: A Coherent Model Lab5
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‹TileLink and Custom Coherence Extensions
  1. Topics
  2. Cache Coherency
  3. Real Protocols
  4. TileLink and Custom Coherence Extensions
  5. TileLink Permissions

Part 8 · Real Protocols · All levels

TileLink Permissions

TileLink conformance levels, the five channels and why E > D > C > B > A, and the None, Branch, Trunk and Tip permissions mapped onto course states.

On this page

    What does a TileLink cache hold instead of M, E, S and I?

    A permission on a position in a tree, not a MESI letter. This lesson uses the SiFive TileLink Specification, version 1.8.1 (27 January 2020), chapters 1, 2, 5 and 9. The specification calls the requesting side of a link the master interface and the managing side the slave interface. On the course model, C0 and C1 are masters and H is the slave that manages X.

    Three conformance levels

    Level

    Adds

    Channels

    TL-UL (Uncached Lightweight)

    Single-beat Get and Put (read and write)

    A and D

    TL-UH (Uncached Heavyweight)

    Multibeat bursts, atomics (ArithmeticData, LogicalData) and hints (Intent)

    A and D

    TL-C (Cached)

    Cache block transfers: Acquire, Probe, Release

    A, B, C, D and E

    Only TL-C keeps cached copies coherent. A TL-UL device such as a timer never caches, so it needs no B, C or E channel. A TL-C agent talking to a TL-UL device must either avoid the advanced features or sit behind an adapter (section 1.1).

    Five channels and a strict priority

    Channel

    Direction

    TL-C use

    Course analogue

    A

    Master to slave

    Acquire: ask for permission and usually data

    Request (GetS, GetM)

    B

    Slave to master

    Probe: take permission away, possibly fetch data

    Forward (Inv, Fwd-GetS, Fwd-GetM)

    C

    Master to slave

    ProbeAck answers a Probe. Release is a voluntary writeback.

    Inv-Ack or Data to H. PutS, PutE, PutM

    D

    Slave to master

    Grant gives permission and data. ReleaseAck acknowledges a Release.

    Data to the requester. Put-Ack

    E

    Master to slave

    GrantAck: the final acknowledgement of a Grant

    The completion message of Part 4

    Section 2.2 fixes the priority A < B < C < D < E and says it must be strictly enforced. Section 5 turns it into forward-progress rules: an agent must eventually accept a presented beat and eventually answer a received request, unless it has a higher-priority message in flight or unanswered. So an agent may block a lower channel while it waits on a higher one, never the other way round. Section 9.2 adds that higher-priority messages must be able to bypass lower-priority ones in the network, even to the same agent.

    This is the request < forward < response rule with one more class. Every response travels on a higher channel than its request: Acquire (A) is answered by Grant (D), Probe (B) by ProbeAck (C), Release (C) by ReleaseAck (D), and Grant (D) by GrantAck (E). A message that an agent receives can therefore only make it wait for messages above it, and E, at the top, waits for nothing.

    Why must E be highest? Section 9.2 says the slave should not issue a Probe for a block while a GrantAck for it is pending. So H holds X's next transaction until GrantAck arrives. If GrantAck could queue behind an Acquire for X on a shared buffer, H would wait for GrantAck, GrantAck would wait for the Acquire, and the Acquire would wait for H: a cycle. Putting GrantAck on the top channel means it always sinks.

    C0 sends Acquire on A, Release and ProbeAck on C, and GrantAck on E to H. H sends Probe on B and Grant and ReleaseAck on D to C0.
    One TL-C link on the course model. C1 has an identical link to H. Priority rises from A to E.

    Permissions: None, Branch, Trunk, Tip

    For one address, all caching agents form a tree rooted at the slave. Section 9.1 names each node's position. The table also gives the accesses allowed, from Table 29 and the section 9.1 text, and says where the two disagree.

    TileLink position

    Meaning in the specification

    Accesses allowed

    Course state

    None

    No cached copy

    None

    I

    Branch

    Copy above the Tip, read-only

    Get

    S

    Trunk

    Copy on the path between the Tip and the root, may be stale. Section 9.1 says it has neither read nor write permission.

    None by the 9.1 definition (the copy may be stale). Table 29 of 1.8.1 lists Get, which contradicts 9.1. Do not serve local reads from a Trunk.

    No leaf equivalent: an inclusive intermediate cache whose child holds the line

    Tip with Branches

    Point of write serialization, copies above it

    Get (Table 29). The 9.1 text says read and write, but a store must first Probe the Branches away, after which this is a Tip with no Branches.

    On the course model, H (with memory) when C0 and C1 both hold Branch: the root is the Tip (Figure 25). No leaf cache state corresponds.

    Tip, no Branches

    Point of memory-access serialization, may hold dirty data

    Get, Put, atomics

    E or M (MESI, MOESI)

    Three points matter when you read traces. First, Tip covers both E and M: the permission says nothing about dirty data. Exactly as H cannot tell E / 0 from M / 1 in the course (exclusive(C0)), a TileLink home cannot tell a clean Tip from a dirty one until the data comes back. Second, the parameters on a link use only N, B and T. Seen from H across one link, T means the master's subtree holds Trunk-or-Tip: the course's exclusive holder. Third, Trunk appears only in a hierarchy; on the two-cache course model the only caching agents are C0 and C1. A cluster cache inside a two-level directory that has passed exclusive permission up to its core is a Trunk.

    Worked snapshots on the course model

    Independent settled snapshots, not a sequence. X started at 0; rows with 1 assume C0 stored 1. The last column gives each cache's TileLink permission.

    Case

    C0 state / value

    C1 state / value

    H directory

    Memory

    TileLink C0, C1

    Uncached

    I / -

    I / -

    U

    0

    N, N

    MESI, C0 exclusive clean

    E / 0

    I / -

    exclusive(C0)

    0

    T, N

    MESI, C0 exclusive dirty

    M / 1

    I / -

    exclusive(C0)

    0

    T, N

    MSI or MESI, shared

    S / 1

    S / 1

    S{C0,C1}

    1

    B, B

    The E and M rows have identical TileLink permissions and identical directory records. The dirty bit lives inside C0's cache, and appears on the wire only when C0 answers a Probe with ProbeAckData or evicts with ReleaseData.

    Permission transfers

    Every TL-C message carries a parameter naming the transition. Section 9.1.4 (Table 31) defines four groups with these 3-bit encodings:

    Group

    Transitions (encoding)

    Meaning

    Carried by

    Grow

    NtoB (0), NtoT (1), BtoT (2)

    Upgrade, naming old and new permission

    AcquireBlock, AcquirePerm

    Prune

    TtoB (0), TtoN (1), BtoN (2)

    Downgrade, naming old and new permission

    ProbeAck, ProbeAckData, Release, ReleaseData

    Report

    TtoT (3), BtoB (4), NtoN (5)

    No change, reports the current permission

    ProbeAck, ProbeAckData, Release, ReleaseData

    Cap

    toT (0), toB (1), toN (2)

    Target only, old permission not named

    ProbeBlock, ProbePerm, Grant, GrantData

    Table 31 calls the downgrade group Prune; the message sections of 9.3 call the same group Shrink. A Probe uses Cap because the home only states a ceiling. Capping above the current permission is allowed and changes nothing, so a toB Probe to a Branch is answered BtoB. A Grant uses Cap and may exceed what the Acquire asked for: an NtoB Acquire answered with a toT Grant is the MESI E grant.

    A leaf cache grows from N to B or T through Acquire and Grant, grows B to T, and is pruned from T to B or N, or B to N, by a Probe or by its own Release.
    TileLink 1.8.1 permissions at one leaf cache, as seen across its link. Simplified: transient waits, Report no-ops and the dirty bit are omitted.
    example.py
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    ORDER = "ABCDE"
    MSGS = {  # message: (channel, possible responses), TileLink 1.8.1 Table 30
        "AcquireBlock": ("A", ["Grant", "GrantData"]), "AcquirePerm": ("A", ["Grant"]),
        "ProbeBlock": ("B", ["ProbeAck", "ProbeAckData"]), "ProbePerm": ("B", ["ProbeAck"]),
        "ProbeAck": ("C", []), "ProbeAckData": ("C", []),
        "Release": ("C", ["ReleaseAck"]), "ReleaseData": ("C", ["ReleaseAck"]),
        "Grant": ("D", ["GrantAck"]), "GrantData": ("D", ["GrantAck"]),
        "ReleaseAck": ("D", []), "GrantAck": ("E", []),
    }
    
    def responses_climb(msgs):
        return all(ORDER.index(msgs[r][0]) > ORDER.index(ch)
                   for ch, rs in msgs.values() for r in rs)
    
    assert responses_climb(MSGS)
    bad = dict(MSGS, Push=("D", ["PushAck"]), PushAck=("B", []))
    assert not responses_climb(bad)   # a response below its request breaks the rule
    
    RANK = {"N": 0, "B": 1, "T": 2}
    GROW = {"NtoB": 0, "NtoT": 1, "BtoT": 2}
    PRUNE = {"TtoB": 0, "TtoN": 1, "BtoN": 2}
    REPORT = {"TtoT": 3, "BtoB": 4, "NtoN": 5}
    def delta(name):
        return RANK[name[3]] - RANK[name[0]]
    assert all(delta(n) > 0 for n in GROW)
    assert all(delta(n) < 0 for n in PRUNE)
    assert all(delta(n) == 0 for n in REPORT)
    # ProbeAck and Release put Prune or Report in one field: encodings must not collide
    assert not set(PRUNE.values()) & set(REPORT.values())
    assert set(GROW.values()) & set(PRUNE.values())   # same codes, so the opcode decides
    
    COURSE = {"I": "N", "S": "B", "E": "T", "M": "T"}
    assert [s for s in COURSE if COURSE[s] == "T"] == ["E", "M"]   # T cannot say clean or dirty
    print("PASS: TileLink responses climb A<B<C<D<E, Prune/Report codes are disjoint, T covers E and M")

    Common pitfall

    Reading Tip or T as M. T is exclusive permission only. Whether memory is stale depends on whether the holder wrote, which TileLink reveals only through ProbeAckData or ReleaseData, just as the course's exclusive(C0) hides E versus M.

    Interview

    Asked why TileLink has five channels, answer with dependencies: each response climbs to a higher channel than its request, an agent may block only lower channels while it waits, and GrantAck on E sinks unconditionally, so no cycle of waits can form.

    Check yourself C0 holds X with Branch permission. H sends ProbeBlock with toB. What does C0 answer and what changes?

    ProbeAck with BtoB from the Report group. A Cap above or equal to the current permission changes nothing, and C0 holds no dirty data as a Branch, so no ProbeAckData is needed. C0 stays S in course terms.

    Related topics

    • Shared course model

    • Next: TileLink transactions

    • The request < forward < response rule

    • Message classes and virtual networks

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    See also

    • Custom Extensions and Their Risks
    • Protocol Comparison Sheet