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Course contents

  • How to Use This Course
  • Reading Path
  • Cache Coherency Glossary
  • The Shared Course Model
  • Cache Coherency Revision Sheet
  • Why Coherence Exists8
  • States and Protocols12
  • Transactions12
  • Races and Controller Design8
    • Transient States and Races
      • Why Transient States Exist
      • Simultaneous Upgrades
      • Racing Requests at the Home
      • Eviction Versus Intervention
    • Controller Resources
  • Progress and the Fabric16
  • Ordering and Synchronization12
  • Performance and Scalability12
  • Real Protocols12
  • SoC Integration12
  • Power, Clocking and Reliability12
  • Verification12
  • Debug and Bring-up12
  • Interview and Design Review17
  • Capstone: A Coherent Model Lab5
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‹Transient States and Races
  1. Topics
  2. Cache Coherency
  3. Races and Controller Design
  4. Transient States and Races
  5. Why Transient States Exist

Part 4 · Races and Controller Design · All levels

Why Transient States Exist

Record pending requests and protected payloads instead of pretending a requested stable state already exists.

On this page

    What must the controller remember while waiting?

    The pilot introduced stable and transient states. Now use them as an engineering record: the requested state, retained bytes, missing responses and release conditions are separate facts. A name such as IM^D is useful only if those facts are defined.

    The cold read miss already traces C0's GetS from X = 0 uncached (MSI): H reads memory, sends Data with S permission, and only that Data makes C0's copy usable. What that trace leaves implicit is the step before the request. C0 first allocates a miss record (an MSHR) and enters IS^D, and only then sends GetS. At that point C0 is IS^D / -, C1 is I / -, H is still U and memory = 0: no message has reached H, so H's entry does not change. The record survives until the grant is delivered.

    An I copy enters IS^D on a local miss and becomes S only on its matching readable Data grant.
    Local states only. What H holds is tracked in H's own record, not in C0's state letter.

    Retained information changes what an event means

    Pending kind

    Retained fact

    Missing fact

    Local restriction

    IS^D

    Requester and line identity

    Readable data and grant

    No load or store to X.

    IM^D

    Store intent and line identity

    Current value and exclusive permission

    No store before the grant.

    SM^D

    Shared data, unless invalidated

    Exclusive permission

    Loads hit, stores stall. An Inv can remove the readable copy.

    MI^A (dirty eviction)

    The dirty line in the WB entry

    Put-Ack from H (H now holds the data)

    Loads and stores to X stall. Do not free the WB entry early.

    In SM^D an incoming Inv removes the read rights but keeps the store intent: the line becomes IM^D. The Primer collects acks at the requester and so uses the names IM^AD and SM^AD. Do not mix the two conventions in one lesson.

    Common pitfall

    Installing the desired stable M state when GetM is sent grants rights before the protocol has established them. Conversely, discarding the pending record when bytes are buffered at H loses the link to the requester that still needs them.

    Interview

    For one transient, name a retained fact, a missing fact and the exact event that completes it. Then explain how a conflicting incoming event would be handled rather than ignored.

    Check yourself After H reads memory, H already has 0. Why does C0 still need IS^D?

    Its own grant has not arrived and it has no usable copy. H's buffered value is not C0's permission. The pending record identifies the response and operation that must still complete.

    Related topics

    • Shared course model

    • Next: an invalidation while waiting

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    See also

    • Racing Requests at the Home
    • Eviction Versus Intervention