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Course contents

  • How to Use This Course
  • Reading Path
  • Cache Coherency Glossary
  • The Shared Course Model
  • Cache Coherency Revision Sheet
  • Why Coherence Exists8
    • Caches and Shared Data
      • Caches, Lines and Write-Back
      • Two Cores Disagree
      • What Coherence Promises
      • The Course Model in Action
    • Permissions and Values
  • States and Protocols12
  • Transactions12
  • Races and Controller Design8
  • Progress and the Fabric16
  • Ordering and Synchronization12
  • Performance and Scalability12
  • Real Protocols12
  • SoC Integration12
  • Power, Clocking and Reliability12
  • Verification12
  • Debug and Bring-up12
  • Interview and Design Review17
  • Capstone: A Coherent Model Lab5
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‹Caches and Shared Data
  1. Topics
  2. Cache Coherency
  3. Why Coherence Exists
  4. Caches and Shared Data
  5. What Coherence Promises

Part 1 · Why Coherence Exists · All levels

What Coherence Promises

Separate the single-writer permission rule, value preservation and the limits of per-location coherence.

On this page

    What contract do the controllers enforce?

    Why are valid state letters insufficient to prove correctness? A machine could grant perfectly exclusive permissions yet hand each new holder an obsolete value. Prerequisite: distinguish usable copies from invalid bits. Coherence needs both compatible permissions and preservation of the latest value across permission changes.

    The single-writer, multiple-reader rule permits either one core with read/write access, or any number of cores with only read access. The data-value rule carries the final value of the previous write epoch into the next epoch, using the initial value if no store has occurred. These are the two invariants of the Primer, second edition, Chapter 2.

    Classify rights and responsibility separately

    The following are independent, settled candidates on the course model, not transitions. X starts at 0 uncached; candidates containing 1 assume that 1 is the most recent accepted store. Epochs are as defined in Two Cores Disagree: a write epoch lasts as long as one cache holds exclusive write permission, even when its core is not executing stores, and idle periods without a writer belong to a read epoch.

    Write epochs contain one M or E holder, while read epochs contain only readers, with O carrying dirty responsibility only in MOESI.
    Permission categories across named protocols. Branches classify snapshots; they do not prescribe a transaction order.

    Protocol / candidate

    C0 state / value

    C1 state / value

    H directory

    Memory

    Why it fits or fails

    MSI: initial idle

    I / -

    I / -

    U

    0

    Zero readers, zero writers; memory authoritative

    MSI or MESI: clean sharing

    S / 1

    S / 1

    S{C0,C1}

    1

    Readers agree; memory current

    E (MESI, MOESI): clean exclusive

    E / 0

    I / -

    exclusive(C0)

    0

    Only C0 may write; memory current now

    MSI, MESI or MOESI: dirty exclusive

    M / 1

    I / -

    exclusive(C0)

    0

    C0 has write permission and dirty responsibility

    MOESI only: dirty sharing

    O / 1

    S / 1

    O: C0, sharers {C1}

    0

    No writer; C0 preserves dirty data for both readers

    Any: lost value

    I / -

    M / 0

    exclusive(C1)

    0

    Illegal if the preceding write epoch ended at 1

    The O entry names C0 as the dirty-responsible holder and lists C1 as a sharer; C0 can read too. O is read-only dirty responsibility, never permission to keep writing beside C1. Neither directory label is a cache state: one exclusive(C0) entry covers both E and M without pretending H observes silent stores.

    Where the promise ends

    The last candidate satisfies exclusive permission but loses the previous value. It therefore fails even without a competing reader. Conversely, correct value transfer says nothing by itself about how accesses to two different addresses are ordered. Coherence supplies a per-location contract; a memory consistency model specifies permitted ordering across operations. Neither cache state nor a fence alone supplies language-level synchronization.

    Common pitfall

    Do not infer that all memory must always be current, or that O is a second writable state. In MSI and MESI, a dirty remote read must make memory current before settling as S / S. MOESI can keep stale memory with O / S. These are different protocol choices.

    Interview

    Give two independent failure examples: M beside S violates permissions even with equal values; a new sole M holder receiving 0 after the last write of 1 violates value preservation. Then state that the contract is per location.

    Check yourself Can O / 1 at C0 and S / 1 at C1 be a legal read epoch with memory = 0?

    Yes, in the named MOESI variant. Both caches may read but neither may write; C0 is responsible for the dirty value. It would not be a valid settled S / S snapshot in this course's MSI or MESI model.

    Related topics

    • Course Model

    • Next: The Course Model in Action

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    See also

    • Caches, Lines and Write-Back