CDC / RDC · All levels
Chip-level RDC Closure: Comparison Matrix
Comparison Matrix for Chip-level RDC Closure.
Comparison matrix
Structural checks and dynamic stress provide different confidence layers.
+------------------+----------------+----------------+----------------+
| Approach | Strength | Weakness | Best when |
+------------------+----------------+----------------+----------------+
| Conservative | safe | extra latency | high-risk crossings |
| Balanced | practical | more setup | most production paths |
| Aggressive | fast schedule | escape risk | late-stage crunch |
| Refactor | structural gain | long cycle | recurring failures |
+------------------+----------------+----------------+----------------+When to choose each approach
Select approach by silicon risk, not only schedule urgency
Interview traps
Global waiver spray
Unproven protocol assumptions
Evidence comparison
CDC/RDC EVIDENCE MATRIX — Chip-level RDC Closure
+-----------------------+----------------------------+----------------------------+---------------------------+
| Evidence | Tells you | Does not prove | Next action |
+-----------------------+----------------------------+----------------------------+---------------------------+
| structural report | crossing topology class | protocol liveness | add assertions/formal |
| reset map | release dependencies | dynamic startup behavior | run reset stress tests |
| formal proof | bounded safety/liveness | real firmware sequence | correlate with simulation |
| simulation stress | observed mode behavior | full state-space closure | target unhit corners |
| waiver log | accepted residual risk | technical correctness | periodic revalidation |
+-----------------------+----------------------------+----------------------------+---------------------------+CDC/RDC deep dive
RDC closure must connect IP assumptions to SoC reality.
Concept diagram
RDC CLOSURE
IP reset intent + SoC sequencing -> structural checks -> dynamic stress -> signoffMetric graph
MILESTONE READINESS
M-2 55%
M-1 82%
M0 100%Reports and artifacts
top-level RDC opens
reset simulation coverage
chip integration blockers
waiver backlog
Mini case study
Each IP was locally clean, but top-level sequencing violation created cross-subsystem boot intermittency.
Debug branches
Audit subsystem assumptions
stress chip-level reset scenarios
close ownership gaps
Senior review question
Ask: what evidence proves this risk is closed for silicon, not just tool-clean?
Key takeaways
State crossing class, assumptions, and owner with every issue.
Run structural and dynamic regressions after each fix.
Common pitfalls
Treating all warnings as equivalent risk.
Waiving issues without containment evidence.
Skipping reset and reconvergence stress after CDC fixes.
Principal CDC/RDC review addendum
Chip-level RDC closure depends on clean reset intent handoff from IPs and alignment between subsystem sequencing assumptions.
Metric: top-level RDC open count, subsystem handoff completeness, integration churn