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Course contents

  • How to Use This Course
  • Reading Path
  • CDC/RDC Glossary
  • CDC/RDC Metrics Reference
  • CDC/RDC Interview Prep
  • CDC/RDC Signoff Cheatsheet
  • Clock Domains and Failure Modes8
  • Metastability and Synchronizers16
  • CDC Protocols and Handshakes16
  • Reconvergence and Gray Coding16
  • Reset Domain Crossing16
  • Architecture and Design Rules16
  • CDC Signoff Methodology24
  • RDC Signoff16
    • RDC Methodology
    • Reset-aware Simulation
    • Chip-level RDC Closure
      • Hierarchical RDC
      • IP Integration Resets
      • Power and Warm-reset Interaction
      • Chip-level RDC Reviews
    • RDC Signoff Dashboard
  • Debug and Case Studies11
  • CDC and RDC Interview Prep30
  • Capstone: Sign Off a Multi-clock Peripheral4
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‹Chip-level RDC Closure
  1. Topics
  2. CDC & RDC
  3. RDC Signoff
  4. Chip-level RDC Closure
  5. IP Integration Resets

Part 8 · RDC Signoff · All levels

IP Integration Resets

Third-party and reused IP reset requirements and checklists.

On this page

    Third-party and reused IP arrives with its own reset architecture, its own assumptions, and documentation of varying honesty. The integrator cannot see inside encrypted or legacy IP, so reset signoff for IP is a contract check: does the documentation state every reset requirement, and does the chip meet all of them?

    The IP reset checklist

    Item

    What good looks like

    If it is missing

    Reset ports and polarity

    Every reset port named with polarity and assertion style.

    Probe the behaviour in simulation; never guess polarity from the name.

    Synchroniser included or required

    States whether release synchronisation is inside the IP or expected outside.

    Assume it is required outside and add it, then verify.

    Minimum assertion time

    A stated number of cycles or time the reset must be held.

    Hold reset conservatively long and confirm in simulation.

    Release ordering

    Which resets must release first and what the IP needs from its neighbours.

    Sequence the IP last out of reset and check its outputs stay safe.

    Reset values of visible state

    Status and configuration registers defined at and after reset.

    Read them back after reset in simulation before relying on them.

    Behaviour during reset

    What outputs drive while reset is asserted.

    Treat outputs as unknown during reset and isolate downstream logic.

    What the checks and the review look for

    Structural checks treat undocumented IP resets as crossings with unknown release: findings, not passes. The review walks the checklist row by row for each IP instance, because two instances of the same IP in different reset domains can need different answers. Reused internal IP gets the same treatment whenever its original assumptions are unavailable or its new context differs.

    Common pitfall

    Copying the reset connection from a previous chip without the checklist reuses an answer to a different question. The old chip met the old requirements; the new connectivity, clocks, and ordering need their own walk through the table.

    Interview

    Expect: how do you handle IP with no reset documentation? Answer: assume the worst on every row, synchronise and sequence conservatively, prove each assumption in simulation, and record the answers as the IP reset contract for the next integrator.

    Check yourself IP documentation does not say whether release synchronisation is inside. What do you do?

    Assume it is required outside: add the synchroniser, verify the release sequence in simulation, and record the decision as the working contract.

    Check yourself The same IP is instantiated in two different reset domains. One checklist walk or two?

    Two. Each instance has different neighbours, ordering, and synchronising clocks, so each needs its own row-by-row check.

    Related topics

    • Hierarchical RDC

    • Chip-level RDC reviews

    • RTL: Reset strategies

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    See also

    • Chip-level RDC Reviews