Chip-level RDC Closure: Inputs & Outputs

Inputs and outputs contract

Inputs & Outputs for Chip-level RDC Closure focuses on top-level RDC open count, subsystem handoff completeness, integration churn. The goal is to convert issue observations into mechanism-backed closure decisions.

Treat CDC/RDC signoff as a contract across architecture, RTL, DV, and signoff governance. Most late surprises are contract mismatches, not tooling gaps.

INPUTS
  - crossing inventory with intent classification
  - reset tree and release dependency model
  - protocol assumptions and assertion package
  - CDC/RDC tool configuration + waiver policy

OUTPUTS
  - severity-tagged open issue list
  - protocol/reset proof evidence
  - owner-assigned closure plan
  - signoff or escalation memo

Crossing sequence

CROSSING FLOW — Chip-level RDC Closure

source clock domain -> launch signal -> crossing structure -> destination sample
      |                    |                 |                    |
   source FF           protocol           sync / fifo         destination FF

Key metric: top-level RDC open count, subsystem handoff completeness, integration churn

Ownership map

OWNERSHIP MAP — Chip-level RDC Closure

artifact                  owner
----------------------    -------------------------
design intent           SoC lead
verification evidence   RDC lead
signoff decision        IP owners

Every open CDC/RDC issue needs one accountable owner before waiver or fix.

CDC/RDC deep dive

RDC closure must connect IP assumptions to SoC reality.

Concept diagram

RDC CLOSURE

IP reset intent + SoC sequencing -> structural checks -> dynamic stress -> signoff

Metric graph

MILESTONE READINESS

M-2 55%
M-1 82%
M0  100%

Reports and artifacts

• top-level RDC opens

• reset simulation coverage

• chip integration blockers

• waiver backlog

Mini case study

Each IP was locally clean, but top-level sequencing violation created cross-subsystem boot intermittency.

Debug branches

• Audit subsystem assumptions

• stress chip-level reset scenarios

• close ownership gaps

Senior review question

Ask: what evidence proves this risk is closed for silicon, not just tool-clean?

Key takeaways

• State crossing class, assumptions, and owner with every issue.

• Run structural and dynamic regressions after each fix.

Common pitfalls

• Treating all warnings as equivalent risk.

• Waiving issues without containment evidence.

• Skipping reset and reconvergence stress after CDC fixes.

Principal CDC/RDC review addendum

Chip-level RDC closure depends on clean reset intent handoff from IPs and alignment between subsystem sequencing assumptions.

Metric: top-level RDC open count, subsystem handoff completeness, integration churn