Chip-level RDC Closure: Software / Programmer View

RTL / implementation view

Reset intent annotations reduce integration ambiguity and false waivers.

What designers feel

• Intermittent sync failure

• mode-dependent startup hangs

RTL structure impact

• state machine handshake discipline

• reset release assumptions

• cross-domain data packaging

Synthesis interaction

• retiming can invalidate implicit assumptions

• lint clean does not imply CDC-safe

RTL-side mitigations

• explicit synchronizer wrappers

• protocol assertions

• reset sequence tests

RTL VIEW — Chip-level RDC Closure
// ensure crossing intent and protocol assumptions are explicit in module contract

Implementation layers touched

CDC/RDC OWNERSHIP LAYERS — Chip-level RDC Closure

layer                 owns                            common failure
------------------    -----------------------------   -----------------------------
design intent         crossing architecture           wrong topology selected
protocol semantics    req/ack, fifo, ordering        liveness/deadlock bugs
reset behavior        assert/deassert sequencing      boot instability
analysis setup        tool rules + waivers            false confidence
signoff governance    risk acceptance + dashboard     stale critical waivers

CDC/RDC deep dive

RDC closure must connect IP assumptions to SoC reality.

Concept diagram

RDC CLOSURE

IP reset intent + SoC sequencing -> structural checks -> dynamic stress -> signoff

Metric graph

MILESTONE READINESS

M-2 55%
M-1 82%
M0  100%

Reports and artifacts

• top-level RDC opens

• reset simulation coverage

• chip integration blockers

• waiver backlog

Mini case study

Each IP was locally clean, but top-level sequencing violation created cross-subsystem boot intermittency.

Debug branches

• Audit subsystem assumptions

• stress chip-level reset scenarios

• close ownership gaps

Senior review question

Ask: what evidence proves this risk is closed for silicon, not just tool-clean?

Key takeaways

• State crossing class, assumptions, and owner with every issue.

• Run structural and dynamic regressions after each fix.

Common pitfalls

• Treating all warnings as equivalent risk.

• Waiving issues without containment evidence.

• Skipping reset and reconvergence stress after CDC fixes.

Principal CDC/RDC review addendum

Chip-level RDC closure depends on clean reset intent handoff from IPs and alignment between subsystem sequencing assumptions.

Metric: top-level RDC open count, subsystem handoff completeness, integration churn