Debug playbook

Debug Playbook for Rows, Columns, and Subarray Granularity focuses on Effective tRCD/tRAS/tRP versus bitline length, wordline length, and local row size per subarray.. The purpose is to turn memory observations into mechanism-backed actions with explicit owners and release-safe validation.

DRAM debug should narrow from broad symptom to one dominant mechanism. Avoid mixed-knob sweeps that produce accidental wins without causal confidence.

1. Freeze workload seed, firmware image, timing profile, and thermal setup.

2. Find first failing transition in command timeline.

3. Classify mechanism: locality loss, legality pressure, queue policy, margin drift, or RAS behavior.

4. Build focused reproducer for top hypothesis.

5. Apply minimal reversible fix and define rollback gate.

6. Re-run full performance + reliability matrix.

Debug decision tree

ROOT CAUSE TREE - Rows, Columns, and Subarray Granularity

Effective tRCD/tRAS/tRP versus bitline length, wordline length, and local row size per subarray. regressed
        |
reproducible with fixed seed?
      /               \
    no                 yes
    |                   |
testbench noise    localize bottleneck
                    /              \
               command path       data path
                 |                  |
             scheduler/FSM      PHY/timing/noise
                 |                  |
             timing limits      training/calibration

Stop at first failing mechanism, then patch and re-measure.

Review memo template

DRAM REVIEW MEMO - DRAM Array Organization / Rows, Columns, and Subarray Granularity

1. Symptom
   - Watched metric: Effective tRCD/tRAS/tRP versus bitline length, wordline length, and local row size per subarray.
   - Failing traffic slice: <workload/phase/class>
   - First failing transition: <row-hit/row-conflict/turnaround/refresh/training>
   - Revision tags: <firmware/controller/timing/board/package>

2. Mechanism hypothesis
   - Primary mechanism: A DRAM array is physically tiled into subarrays so each local wordline and bitline segment stays within a manageable RC envelope. Longer rows increase row-buffer capacity but lengthen wordline propagation and bitline loading, which increases ACTIVATE latency and sensing energy. Narrower subarrays improve local timing and noise margin but add peripheral overhead (local decoders, isolation devices, sense resources), reducing area efficiency. Column muxing then trades pin bandwidth and internal burst granularity against peripheral complexity. The final row/column partition is therefore not an abstract addressing choice; it is a first-order physical design knob that sets access latency, activation current profile, and manufacturability.
   - Competing hypotheses: <mapping, scheduling, PHY margin, SI/PI, reliability policy>
   - Missing evidence: <command trace, queue snapshot, lane margins, CE/UE logs>

3. Proposed action
   - Smallest reversible change: <policy/register/firmware/flow>
   - Expected movement: <p99 latency, effective bandwidth, stability>
   - Regression risk: fairness, thermal drift, training robustness, field reliability

4. Signoff
   - Re-run artifact: Subarray sizing tradeoff sheet: row length, bitline RC, timing deltas, and die-area overhead.
   - Required owners: DRAM architect, circuit designer, layout/physical designer, memory controller owner, product reliability owner
   - Final decision: ship, bounded rollout, rollback, or escalate

DRAM deep dive

Cell-array and subarray organization determines bitline delay, sensing margin, and locality-sensitive energy cost.

Concept diagram

ARRAY ORGANIZATION VIEW

rows x columns -> mats/subarrays -> local sense amps -> global I/O
physical distance shapes timing and energy

Metric graph

ARRAY ACCESS COST SHARE

bitline settle delay   ██████
sense/restore time     █████
global routing overhead ███

Reports and artifacts

• subarray toggle heatmap

• sense-amplifier utilization report

• bitline RC delay audit

• wordline coupling checklist

Mini case study

A dense address remap increased long-bitline activations, creating extra tRCD guardband and persistent tail-latency drift.

Debug branches

• Map hot addresses to mats and subarray boundaries

• Inspect sense-margin behavior under temperature corners

• Evaluate row-mapping changes before voltage retuning

Senior review question

Ask: which latency, bandwidth, and reliability evidence proves this DRAM topic is closed under real traffic?

Key takeaways

• Always tie controller and PHY counter shifts to application latency and throughput outcomes.

• Lock firmware timing profile, thermal condition, and DIMM state before comparing DRAM captures.

Common pitfalls

• Chasing peak bandwidth while ignoring p99 latency and fairness tails.

• Changing timing guardbands without separating SI noise from scheduling issues.

• Declaring closure without reliability gates, fault injection, and regression replay.

Principal DRAM review addendum

Rows, Columns, and Subarray Granularity should be read as an end-to-end memory behavior, not as a single block definition. A production DRAM subsystem reflects interactions between array physics, command legality, scheduler policy, PHY margin, and reliability controls before software experiences final latency or bandwidth.

A DRAM array is physically tiled into subarrays so each local wordline and bitline segment stays within a manageable RC envelope. Longer rows increase row-buffer capacity but lengthen wordline propagation and bitline loading, which increases ACTIVATE latency and sensing energy. Narrower subarrays improve local timing and noise margin but add peripheral overhead (local decoders, isolation devices, sense resources), reducing area efficiency. Column muxing then trades pin bandwidth and internal burst granularity against peripheral complexity. The final row/column partition is therefore not an abstract addressing choice; it is a first-order physical design knob that sets access latency, activation current profile, and manufacturability. DRAM inefficiency is multiplicative: one extra ACTIVATE, one unnecessary turnaround, one weak lane margin, or one refresh collision repeated across billions of accesses can dominate product tail latency and power.

Use Effective tRCD/tRAS/tRP versus bitline length, wordline length, and local row size per subarray. as the opening signal, not the conclusion. A metric move only becomes actionable when paired with workload context, command traces, training telemetry, and evidence artifacts such as Subarray sizing tradeoff sheet: row length, bitline RC, timing deltas, and die-area overhead..

Array organization sets the geometry of latency, bandwidth, and power before scheduler policy is even considered. Senior review quality comes from proving a complete chain: request pattern -> memory-state transition -> bottleneck mechanism -> smallest owner fix -> regression-safe validation.

Review discipline should enforce a single causal chain: traffic pattern -> command-level behavior -> array/PHY effect -> measured product impact. That chain prevents tuning folklore from replacing evidence.