DRAM Fundamentals & Cell Physics: Tricky Q&A

[INT][DRAM][DRAM-FOUNDATIONS]

Q: Why is a DRAM read called destructive, and what exact operation repairs the data?

A:
When the wordline turns on, cell charge redistributes onto a much larger bitline capacitance, collapsing the original storage-node voltage toward the bitline midpoint. The sense amplifier then resolves the small differential and, while wordline remains asserted, drives the bitline back to a full level to restore charge into the capacitor. That restore phase is the repair step; ending ACTIVATE too early causes under-restored cells and retention loss.

FOLLOW-UP TRAP: Assuming data is preserved in the capacitor throughout the read and restore is optional.

[INT][DRAM][DRAM-FOUNDATIONS]

Q: What physical reason makes tRCD and tRP non-zero even with an ideal digital command bus?

A:
Both timings are bounded by analog RC and regenerative settling. tRCD covers wordline propagation, charge sharing, and minimum sense differential before safe data capture. tRP covers turning off cell access, equalizing paired bitlines to the precharge point, and damping residual imbalance so the next ACTIVATE starts from symmetric initial conditions. Faster command toggling cannot bypass these internal array settling requirements.

FOLLOW-UP TRAP: Treating JEDEC timings as protocol padding rather than array-physics constraints.

[INT][DRAM][DRAM-FOUNDATIONS]

Q: Why can two DRAM parts with the same nominal refresh interval show different field retention failures?

A:
Retention failures are tail-driven and process dependent. Two parts may share the same average leakage yet differ in weak-cell distribution, variable-retention behavior, and disturbance susceptibility. Packaging thermal profile, workload row locality, and controller refresh scheduling (postpone/pull-in behavior) further change effective risk. Qualification must therefore analyze retention CDF tails and disturbance interactions, not just nominal tREFI compliance.

FOLLOW-UP TRAP: Comparing only average retention or only nominal tREFI values across products.

[INT][DRAM][DRAM-FOUNDATIONS]

Q: How does sense-amp offset interact with bitline capacitance and cell capacitance in read margin?

A:
The initial read signal is approximately proportional to Ccell/(Ccell + Cbitline) times stored voltage swing. Larger bitline capacitance or smaller cell capacitance reduces the developed differential, forcing tighter sense-amp offset/noise requirements and longer sensing time. Conversely, better Ccell/Cbit ratio or lower bitline loading improves detectability and timing margin. Read margin is therefore co-optimized across layout RC, capacitor technology, and sense-latch mismatch control.

FOLLOW-UP TRAP: Optimizing sense amp in isolation without accounting for the Ccell-to-Cbitline ratio.

WORKLOAD -> DRAM SYMPTOM -> TIMING/QUEUE METRIC -> ROOT CAUSE -> FIX -> REGRESSION

DRAM ACCESS PRIMITIVES

request -> ACT (open row) -> READ/WRITE burst -> PRE (close row)
bank groups + refresh windows bound true throughput