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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
  • Interview Prep: Puzzle Rounds5
  • DV Puzzle Cheatsheet
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‹DV Interview Puzzles
  1. Topics
  2. DV Interview Puzzles
  3. DV Puzzle Cheatsheet

VLSI DV Interview Puzzles · All levels

DV Puzzle Cheatsheet

Dense reference of the rules behind the most common DV interview puzzles.

On this page

    Language gotchas

    • == / != are 4-state and can return x; use === / !== for exact X/Z compare.

    • bit (2-state) collapses X/Z to 0; logic (4-state) preserves them.

    • >>> is arithmetic only on signed operands; >> always zero-fills.

    • Any unsigned operand makes the whole expression unsigned before the operator runs.

    • $cast checks runtime type; a static handle assignment can compile yet be illegal at runtime.

    Process & timing

    • join resumes after all children; join_any after one; join_none immediately.

    • Pair join_any/join_none with disable fork or explicit sync or you leak threads.

    • Nonblocking (<=) updates in the NBA region; read-after-NBA in the same step sees the old value.

    • Clocking block inputs sample on the previous edge (input skew); outputs drive with output skew.

    Randomization & constraints

    • Constraints solve as a system, not top-to-bottom; order does not imply precedence.

    • dist := gives each listed value that weight; :/ splits the weight across the range.

    • solve...before only biases distribution; it never changes the legal solution set.

    • An over-constrained randomize() returns 0 and leaves variables unchanged.

    Assertions & coverage

    • |-> is overlapped (same cycle); |=> is non-overlapped (next cycle).

    • An assertion whose antecedent never holds is a vacuous pass, not a real pass.

    • $past/$rose/$fell sample in the preponed region relative to the assertion clock.

    • Unreached bins, wrong sample event, or ignore/illegal bins are the usual coverage-closure traps.

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    See also

    • How to Use This Puzzle Bank
    • SystemVerilog Language Puzzles
    • Difficulty Guide