VLSI DV Interview Puzzles · All levels
Interview-Day Tips
Concrete tactics for SystemVerilog/DV puzzle rounds.
During a puzzle round
State your assumptions about types, widths, and clocking before you answer.
Trace value-by-value for short snippets; draw the scheduling regions for timing puzzles.
If you are unsure, narrate the rule you are applying — partial credit is real.
When you spot the trap, say it explicitly: 'the catch here is 2-state collapses X to 0'.
Common pitfalls
Guessing an output without tracing it.
Confusing coherence of intuition with correctness of semantics.
Forgetting that simulators differ from the LRM only in undefined cases.