Skip to content
DenseChip
Learn
PracticeCode labInterview

DenseChip

Navigate

Menu

LearnPracticeCode labInterview

Tools

All toolsSV editorCode repoResume
DenseChip

Practice, courses, and chip-design tools in one focused workspace.

LearnPracticeCode labInterviewToolsLearning paths

© 2026 DenseChip

AboutContactPrivacyTerms
Skip to lesson

Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
    • Datatype and Bit Puzzles
      • X-Bit Comparisons and Mixed Arithmetic
      • Signed vs Unsigned Comparison Trap
      • Type Cast Controls Sign Extension
      • Signed Part-Select Is Still Unsigned
      • X Collapse into 2-State `int`
      • Case Equality vs Wildcard Equality
    • Fork Join Puzzles
    • Queue and Array Puzzles
    • String and Casting Puzzles
    • SystemVerilog Language Puzzles: Tricky Q&A
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
  • Interview Prep: Puzzle Rounds5
  • DV Puzzle Cheatsheet
Loading lesson

‹Datatype and Bit Puzzles
  1. Topics
  2. DV Interview Puzzles
  3. SystemVerilog Language Puzzles
  4. Datatype and Bit Puzzles
  5. X-Bit Comparisons and Mixed Arithmetic

VLSI DV Interview Puzzles · All levels

X-Bit Comparisons and Mixed Arithmetic

Predict each display line exactly, including where x appears, and explain why.

On this page

    Puzzle

    Difficulty: Easy · Puzzle 1 of 6 · Topic: Datatype and Bit Puzzles

    Predict each display line exactly, including where x appears, and explain why.

    Code

    p1.sv
    1
    2
    3
    4
    5
    6
    7
    8
    9
    10
    11
    12
    13
    module p1;
      logic [3:0] a = 4'b1x01;
      bit   [3:0] b = 4'b1x01;
      logic signed [3:0] s = 4'b1100; // -4
      logic [7:0] u = 8'd250;
      initial begin
        $display("eq=%b", (a == 4'b1001));
        $display("caseeq=%0d", (a === 4'b1x01));
        $display("b=%b", b);
        $display("s>>>1=%0d s>>1=%0d", (s >>> 1), (s >> 1));
        $display("mix=%0d", u + (-8'sd10));
      end
    endmodule

    Hint

    Treat each expression independently: comparison operator, storage type, and shift operator each have different rules. The last line is a signed/unsigned promotion puzzle.

    Step-by-step solution

    Diagram
    1) `a == 4'b1001` returns x because `a` contains an unknown bit that affects logical equality.
    2) `a === 4'b1x01` returns 1 because case equality matches X/Z explicitly.
    3) `b` is 2-state, so assignment collapses x to 0 and prints 1001.
    4) `s` is -4; arithmetic shift `>>> 1` gives -2, while logical shift `>> 1` zero-fills and gives +6.
    5) In `u + (-8'sd10)`, unsigned `u` forces unsigned arithmetic at 8 bits, so 250 + 246 wraps to 240.

    Answer

    Answer: eq=x, caseeq=1, b=1001, s>>>1=-2 s>>1=6, mix=240

    Why candidates get it wrong

    Candidates often assume `logic` behaves like `bit`, and assume `>>` is arithmetic on signed values.

    Interviewer follow-up

    How would the `mix` result change if you wrote `$signed(u) + (-8'sd10)`?

    Related topics

    • Back to Datatype and Bit Puzzles

    • SystemVerilog Language Puzzles section

    Previous

    4 / 210

    Next: Interview-Day Tips

    Up next

    Up nextInterview-Day Tips

    Sign in to save progress

    Practice this lessonReport an error

    See also

    • Signed vs Unsigned Comparison Trap
    • Type Cast Controls Sign Extension
    • Signed Part-Select Is Still Unsigned