X-Bit Comparisons and Mixed Arithmetic

Puzzle

Difficulty: Easy · Puzzle 1 of 6 · Topic: Datatype and Bit Puzzles

Predict each display line exactly, including where x appears, and explain why.

Code

module p1;
  logic [3:0] a = 4'b1x01;
  bit   [3:0] b = 4'b1x01;
  logic signed [3:0] s = 4'b1100; // -4
  logic [7:0] u = 8'd250;
  initial begin
    $display("eq=%b", (a == 4'b1001));
    $display("caseeq=%0d", (a === 4'b1x01));
    $display("b=%b", b);
    $display("s>>>1=%0d s>>1=%0d", (s >>> 1), (s >> 1));
    $display("mix=%0d", u + (-8'sd10));
  end
endmodule

Hint

Treat each expression independently: comparison operator, storage type, and shift operator each have different rules. The last line is a signed/unsigned promotion puzzle.

Step-by-step solution

1) `a == 4'b1001` returns x because `a` contains an unknown bit that affects logical equality.
2) `a === 4'b1x01` returns 1 because case equality matches X/Z explicitly.
3) `b` is 2-state, so assignment collapses x to 0 and prints 1001.
4) `s` is -4; arithmetic shift `>>> 1` gives -2, while logical shift `>> 1` zero-fills and gives +6.
5) In `u + (-8'sd10)`, unsigned `u` forces unsigned arithmetic at 8 bits, so 250 + 246 wraps to 240.

Answer

Answer: eq=x, caseeq=1, b=1001, s>>>1=-2 s>>1=6, mix=240

Why candidates get it wrong

Candidates often assume `logic` behaves like `bit`, and assume `>>` is arithmetic on signed values.

Interviewer follow-up

How would the `mix` result change if you wrote `$signed(u) + (-8'sd10)`?

Related topics

• Back to Datatype and Bit Puzzles

• SystemVerilog Language Puzzles section