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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
    • Datatype and Bit Puzzles
    • Fork Join Puzzles
    • Queue and Array Puzzles
      • Queue Mutation Plus Dynamic Resize
      • Queue Assignment Copies by Value
      • Pop from Empty Queue
      • Dynamic Array Resize with Class Handles
      • Associative Array Iteration Order
      • Locator Methods Return New Queues
    • String and Casting Puzzles
    • SystemVerilog Language Puzzles: Tricky Q&A
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
  • Interview Prep: Puzzle Rounds5
  • DV Puzzle Cheatsheet
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‹SystemVerilog Language Puzzles
  1. Topics
  2. DV Interview Puzzles
  3. SystemVerilog Language Puzzles
  4. Queue and Array Puzzles

VLSI DV Interview Puzzles · All levels

Queue and Array Puzzles

These puzzles focus on mutable collection semantics that cause real testbench bugs: index shifting, resize copy rules, value-vs-handle behavior, and associative iteration. The goal is to reason about exact final state after each operation, not just API names.

  • 6topics
  • 6lessons

Topics in this section

  1. 1Queue Mutation Plus Dynamic Resize1 lesson
  2. 2Queue Assignment Copies by Value1 lesson
  3. 3Pop from Empty Queue1 lesson
  4. 4Dynamic Array Resize with Class Handles1 lesson
  5. 5Associative Array Iteration Order1 lesson
  6. 6Locator Methods Return New Queues1 lesson
On this page

    About this puzzle set

    These puzzles focus on mutable collection semantics that cause real testbench bugs: index shifting, resize copy rules, value-vs-handle behavior, and associative iteration. The goal is to reason about exact final state after each operation, not just API names.

    Puzzles in this topic

    Diagram
    1. Queue Mutation Plus Dynamic Resize  [Easy]
    2. Queue Assignment Copies by Value  [Easy]
    3. Pop from Empty Queue  [Medium]
    4. Dynamic Array Resize with Class Handles  [Hard]
    5. Associative Array Iteration Order  [Medium]
    6. Locator Methods Return New Queues  [Hard]

    Work each puzzle before reading the solution: predict the exact output or answer, name the rule that governs it, then check yourself.

    SV scheduling regions at puzzle scale

    Diagram
    SYSTEMVERILOG EVENT REGIONS (SIMPLIFIED ORDER)
    
    time slot T
       |
       +--> ACTIVE   : blocking statements, RHS sampling
       +--> INACTIVE : #0 queued work
       +--> NBA      : non-blocking LHS updates commit
       +--> OBSERVED : assertions sample stable design values
       +--> REACTIVE : testbench/program reaction code
    
    If behavior looks impossible, ask: "Which region saw which value?"

    Related topics

    • SystemVerilog Language Puzzles section

    • VLSI DV Interview Puzzles hub

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    See also

    • Datatype and Bit Puzzles
    • Fork Join Puzzles
    • String and Casting Puzzles