Interview-grade puzzles on SystemVerilog scheduler regions, race analysis, clocking block semantics, and semaphore/mailbox deadlocks. Each puzzle mirrors scenarios seen in real UVM benches and focuses on cycle-accurate reasoning under pressure.
Event Scheduling Puzzles — 6 puzzles
Race Condition Puzzles — 6 puzzles
Clocking Block Puzzles — 6 puzzles
Semaphore & Mailbox Puzzles — 6 puzzlesOpen each topic and attempt every puzzle cold, writing your predicted answer first.
Only then read the step-by-step solution and confirm the exact answer.
Re-read the 'why candidates get it wrong' note — that is the actual interview signal.
Finish with the section Q&A to rehearse explaining the rule out loud.