VLSI DV Interview Puzzles · All levels

#0 Monitor Is Still Before NBA

Does adding #0 before compare fix the previous race? Predict mismatch behavior.

Puzzle

Difficulty: Medium · Puzzle 4 of 6 · Topic: Race Condition Puzzles

Does adding #0 before compare fix the previous race? Predict mismatch behavior.

Code

systemverilog
module tb;
  bit clk = 0;
  bit d = 1;
  bit q = 0;
  always #5 clk = ~clk;

  always @(posedge clk) q <= d;

  always @(posedge clk) begin
    #0;
    if (q !== d)
      $display("[%0t #0 CHECK] mismatch q=%0b d=%0b", $time, q, d);
  end

  initial begin
    repeat (2) @(posedge clk);
    $finish;
  end
endmodule

Hint

#0 shifts active to inactive, but NBA is still later.

Step-by-step solution

diagram
1) q<=d is scheduled in active at each edge.
2) Monitor resumes in inactive due to #0 and checks q before NBA commit.
3) At t=5 it still sees q=0, d=1 and prints mismatch.
4) #0 changed region but not enough to see NBA-updated state.

Answer

Answer: No fix. Mismatch still appears at t=5 because #0 checks in inactive, which is before NBA.

Why candidates get it wrong

Using #0 as a generic race cure is unreliable and often wrong.

Interviewer follow-up

What region-safe alternatives can a UVM monitor use for cycle-accurate sampling?

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