VLSI DV Interview Puzzles · All levels
Concurrency & Timing Puzzles: Tricky Q&A
Rapid-fire interview Q&A for Concurrency & Timing Puzzles.
Section Q&A
Rapid-fire questions an interviewer asks around Concurrency & Timing Puzzles. Answer out loud, then check yourself.
Q1. Why can an observed-region assertion still report old signal relationships after NBAs run?
Answer: Because concurrent assertions sample in preponed. Observed-region evaluation uses those earlier sampled values, so it does not automatically reflect same-edge post-NBA state.
Trap: Confusing evaluation region with sampling region.
Q2. What is the real issue when two posedge processes write the same variable in active region?
Answer: It is a scheduler race with undefined process ordering, so results are nondeterministic by language semantics. The robust fix is single-writer ownership with deterministic staging.
Trap: Treating it as a seed problem instead of a race.
Q3. In `input #1step output #0`, why is same-cycle monitor visibility often wrong?
Answer: Input sampling occurs one step before the edge while output drive occurs at the edge. A flopped DUT response is therefore observed on a later sample, typically next cycle.
Trap: Assuming all operations under `@(cb)` share one atomic instant.
Q4. What deadlock pattern appears most in semaphore + mailbox testbench code?
Answer: A thread holds semaphore ownership and then blocks on mailbox put/get while another thread needs that same semaphore to make mailbox progress. This circular wait hangs silently.
Trap: Increasing mailbox depth without fixing lock hold scope.